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模擬與數(shù)字電路 Analog and Digital Circuits,17_時(shí)序邏輯電路(4),1,主要內(nèi)容,數(shù)碼管動(dòng)態(tài)顯示 按鍵/開關(guān)去抖動(dòng) 數(shù)字系統(tǒng)結(jié)構(gòu) 時(shí)序二進(jìn)制乘法器 寄存器組,2,Nexys-3基本輸入/輸出,開關(guān)/按鍵 BTN按下為1 SW撥到上為1 LED指示燈 LD=1時(shí)點(diǎn)亮 7段數(shù)碼管 AN=0使能相應(yīng)數(shù)位 CA~CG：字形碼，0顯示相應(yīng)段(共陽極),3,Nexys-2基本輸入/輸出,開關(guān)/按鍵 BTN按下為1 SW撥到上為1 LED指示燈 LD=1時(shí)點(diǎn)亮 7段數(shù)碼管 AN=0使能相應(yīng)數(shù)位 CA~CG：字形碼，0顯示相應(yīng)段(共陽極),4,數(shù)碼管動(dòng)態(tài)顯示,4位7段 數(shù)碼 顯示 接口,8,DG0,8,DG1,8,DG2,8,DG3,Clk,AN0,AN1,AN2,8,AN3,DG,5,按鍵/開關(guān)去抖動(dòng),輸入 整形 電路,In,Clk,Ol,Op,若In≠Ol，則Cnt計(jì)數(shù)，否則清零 若Cnt=N，則Ol=in，Cnt=0 若Cnt=N且In=1，則Op=1 若Op=1，則Op=0,抖動(dòng)持續(xù)時(shí)間一般在5～10ms,6,數(shù)字系統(tǒng)結(jié)構(gòu),數(shù)字系統(tǒng) 由若干邏輯功能部件構(gòu)成，按一定順序處理數(shù)字信號(hào)的電路 從結(jié)構(gòu)上劃分為數(shù)據(jù)通路和控制單元兩部分 數(shù)據(jù)通路(Data Path) 數(shù)據(jù)在被處理過程中經(jīng)過的路徑 控制單元 (Control Unit) 控制數(shù)據(jù)通路中數(shù)據(jù)的流動(dòng)方向和次序,7,示例1 — 時(shí)序二進(jìn)制乘法器,X，Y：輸入數(shù)據(jù)，被乘數(shù)和乘數(shù)，4位無符號(hào)二進(jìn)制數(shù) Z：輸出數(shù)據(jù)，8位積 Start：控制輸入，啟動(dòng)乘法運(yùn)算，高電平有效 Reset：控制輸入，復(fù)位，高電平有效 Done：狀態(tài)輸出，運(yùn)算結(jié)束指示，高電平有效 Clk：時(shí)鐘輸入,,Start,,Reset,4位乘法器,,,4,Y,,,4,X,,,8,Z,,Done,,Clk,8,乘法運(yùn)算過程,X2,X3,X0,X1,Y2,Y3,Y0,Y1,×,,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,,Z2,Z3,Z0,Z1,Z6,Z7,Z4,Z5,+,(當(dāng)Yi =1),? ? ? ? =,X3X2X1X0,(當(dāng)Yi =0),0 0 0 0,,手工運(yùn)算過程,Z = X × Y,9,乘法器結(jié)構(gòu),10,乘法器結(jié)構(gòu)(續(xù)),11,乘法器控制單元,狀態(tài)圖,,Start,,Reset,Clk,,控制單元,,,,,,Init,Add,,E,,B[0],Cnt,Shr,Done,Init: D?X, B?Y, T?0 , A?0, C?0,Cnt: T?T-1,Add: {C, A}?A+D,Shr: {C, A, B}?{C, A, B}1 , C?0,12,乘法器控制單元(續(xù)1),狀態(tài)表,Reset,Start,B[0],E,Sn,Sn+1,Done,Init,Add,Shr,Cnt,,1,,x,x,x,x,S0,0,0,0,0,1,,0,0,x,x,S0,0,0,0,0,1,S0,0,1,x,x,S1,1,0,0,0,1,S0,0,X,0,x,0,0,0,1,0,0,X,1,x,S2,0,1,0,1,0,S1,S2,S1,0,X,x,0,0,0,1,0,0,0,X,x,1,S0,0,0,1,0,0,S2,S1,S2,,,13,乘法器時(shí)序圖,,,,,,,,,clk,Start,,S0,,,Init,State,,Cnt,Add,,Shr,S1,S2,S1,S2,S1,S2,,,?,D,,?,B,,?,A,,?,T,1111,1011,00,0000,C,Done,,11,10,01,1101,0110,1111,0111,0110,1011,,E,,,?,?,,14,Verilog描述二進(jìn)制乘法器,module binary_multiplier (x, y, z, start, done, reset, clk); output [7:0] z; output done; input [3:0] x, y; input start, reset, clk; reg [3:0] a, b, d; reg c; reg [1:0] state, next_state, t; parameter S0=2’b00, S1=2’b01, S2=2’b10; wire e; assign e = ~|t; assign z = {a, b};,15,Verilog描述二進(jìn)制乘法器(續(xù)1),//state register always @(posedge clk or posedge reset) begin if (reset) state = S0; else state = next_state; end assign done = (state == S0); //next state function always @(start or e or state) begin case (state) S0: if(start) next_state = S1; else next_state = S0; S1: next_state = S2;,16,Verilog描述二進(jìn)制乘法器(續(xù)2),S2: if (!e) next_state = S1; else next_state = S0; default next_state = S0; endcase end //datapath function always @(posedge clk) begin case (state) S0: if (start) begin d = x; b = y; a = 4’d0; c = 1’b0; t = 2’b0; end,17,Verilog描述二進(jìn)制乘法器(續(xù)3),S1: begin t = t - 2’b01; if (b[0]) {c, a} = a + d; end S2: begin a = {c, a[3:1]}; b = {a[0], b[3:1]}; c = 1’b0; end endcase end endmodule,18,乘法器仿真波形,19,寄存器之間傳輸數(shù)據(jù) 每個(gè)寄存器的數(shù)據(jù)輸入處配置多路數(shù)據(jù)選擇器(MUX) 每個(gè)寄存器的輸出數(shù)據(jù)連接到所有MUX 靈活實(shí)現(xiàn)多個(gè)數(shù)據(jù)同時(shí)傳送,寄存器傳送,L0,L1,L2,,R0,Ld,,,R1,Ld,,,R2,Ld,,,,,; S0=1, L0=1 ; S1=0, L1=1,,,,20,,BUS，多個(gè)部件共享用于傳輸數(shù)據(jù)的導(dǎo)線 每次只能傳送一個(gè)數(shù)據(jù),總線,R0 ? R1,; S=1, L0=1,L0,,n,R0,Ld,,,,S,,MUX,S,0,1,,,,2,,,n,,,n,,,L1,,n,R1,Ld,,,,n,,L2,,n,R2,Ld,,,,n,,,,,,,2,R0 ? R1,; E1=1, L0=1,; E0=0, E2=0,21,寄存器組,也稱寄存器堆，或者寄存器文件(Register File) 例如，有3個(gè)讀寫端口的2m個(gè)n位寄存器，其中 D端口供寫 DA：寄存器地址 D：寫入數(shù)據(jù) WE：寫使能 A、B端口供讀 AA、BA：寄存器地址 A、B：讀出數(shù)據(jù),22,,M U X,0 1 2 3,,,,,,,,R0,,,D,E,,R1,,,,D,E,R2,,,,D,E,R3,,,D,E,M U X,0 1 2 3,,,,,,,,,,,,Decoder,0 1 2 3,E,,,,,,A,,,,A,B,D,DA,AA,BA,WE,,2,,n,,2,,2,,n,,n,,n,,n,,n,,n,寄存器組的MUX實(shí)現(xiàn),3端口4×n寄存器組,23,寄存器組的三態(tài)門實(shí)現(xiàn),3端口4×32寄存器組,24,ALU,算術(shù)邏輯單元(Arithmetic Logic Unit) 設(shè)計(jì)8位ALU,ALU功能表,25,示例—數(shù)據(jù)通路,寄存器組 8個(gè)8位寄存器，記為R0~R7 ALU為前例 MEM為存儲(chǔ)器 DI/DO: 輸入/輸出數(shù)據(jù) MA: 地址 MW: 寫使能,Register File,A,B,D,DA,AA,BA,WE,,,8,,,8,,,8,,,3,,,,,3,,,0 1 MUX,,,8,,,,,0 1 MUX,,,,,,,8,MEM,,,DI,DO,MW,MA,,,,,,8,,8,,,4,V,C,N,Z,S,,,3,4,K,,MB,,MD,R0 ? R1-R2,; AA=1, BA=2, MB=1,X,Y,H,F,ALU,; S=5, MD=0,; DA=0, WE=1,26,The End,27,