基于單片機的檔案庫房溫濕度監(jiān)控系統(tǒng)設計,基于,單片機,檔案,庫房,溫濕度,監(jiān)控,系統(tǒng),設計 畢 業(yè) 設 計（論 文）任 務 書 設計（論文）題目：基于單片機的檔案庫房溫濕度監(jiān)控系統(tǒng) 學生姓名： 發(fā)任務書日期：年月日 任務書填寫要求 1．畢業(yè)設計（論文）任務書由指導教師根據(jù)各課題的具體情況填寫，經(jīng)學生所在專業(yè)的負責人審查、系 （院）領導簽字后生效。此任務書應在畢業(yè)設計（論文）開始前一周內填好并發(fā)給學生。 2．任務書內容必須用黑墨水筆工整書寫，不得涂改或潦草書寫；或者按教務處統(tǒng)一設計的電子文檔標準格式 （可從教務處網(wǎng)頁上下載）打印，要求正文小4號 體，1.5 ， 打印在 上 。 3．任務書內填寫的內容，必須 學生畢業(yè)設計（論文） 的情況 一 ， ，應 經(jīng) 所在專業(yè) 系（院） 領導審 后 可 填寫。 4．任務書內 學院 、 專業(yè) 名?的填寫，應寫￠文￡?，不?寫￥字?§。學生的 學號 要寫 ￡號，不?currency1寫'后2“或1“￥字。 5．任務書內 要??文? 的填寫，應按fifl –??學院·?畢業(yè)設計（論文） 寫???的要求書寫。 6． 年月日 日期的填寫，應 按fi?標GB/T 7408—94fl￥據(jù)” ?…格式、‰ ?…、日期 ? `′????的要求，一ˉ用?˙¨￥字書寫。 2002年4月2日 或 2002-04-02”。 畢 業(yè) 設 計（論 文）任 務 書 1．·畢業(yè)設計（論文）課題應??的目的： ??ˇ的發(fā)—人 生 生 ￠所 的 要求 ，? 的a庫 ， ??、??、?o、? a庫日 工 的 要內容， a庫 的 要指標。 ? ? 的?用 工 可??。? 日 工 的? ， 要 題 強a庫內溫度與濕度 的監(jiān)測工 。但傳統(tǒng)的 ? 用與濕度`、毛發(fā)濕度`、雙 屬式測 計 濕度試 測試器材，通 人工 檢測， 不符合溫度 濕度要求的庫房 通風、去濕 降溫 工 。這種人工測試 ?費?費力、效率低， 且測試的溫度 濕度誤差大， 機?大。?此我 要一種造價低廉、?用 便且測 準確的溫濕度測 儀。 由此 的基于單片機的溫濕度測 儀開始出現(xiàn)在了人 的生 生 ￠， ? 不斷的發(fā)— 將被大部分人所 受?！ふn題設計一個溫濕度監(jiān)測系統(tǒng)，用于檔案庫房的溫濕度監(jiān)測，提醒庫 員通風或除濕，溫濕度傳感器 采用DTH11型傳感器， 一種溫濕度一體的￥字單總線傳感器， 測 精度 且 ·較低，適合普通檔案 庫房?用，顯′器采用12864液晶顯′器。以單片機?控制核心，外 硬件電路，將溫濕度顯′ ￥字控制 集 于一體。實現(xiàn) （減）溫、 （除）濕的智?控制。 2．·畢業(yè)設計（論文）課題任務的內容 要求（包括原始￥據(jù)、?術要求、工 要求 ）： 1. 用圖書館的書籍 網(wǎng)絡 源查閱 單片機監(jiān)控溫濕度 內容的書籍 論文，依據(jù)要求 溫濕度 采集模塊的設計；溫濕度顯′模塊的設計。 2. 設計要求設計 要包括硬件電路的設計 系統(tǒng)軟件的設計。 硬件電路 要包括單片機、溫濕度傳感器、顯′模塊、報警器以 控制設 5部分。 ￠由DHT11溫濕度 傳感器 12864液晶顯′器模塊構 系統(tǒng)顯′模塊；測溫濕度控制電路由溫濕度傳感器 預設溫度值比較報 警電路組 ；用戶根據(jù) 要預先輸入預設值， 實際測 的溫濕度不符合預設的溫濕度標準?，發(fā)出報警‰號 （蜂鳴器蜂鳴），啟動 應控制。 軟件部分包括了 程序、顯′子程序、測溫濕度子程序。 3.基·功? ? 檢測溫度、濕度 顯′溫度、濕度 控制溫度、濕度 ? ? 畢 業(yè) 設 計（論 文）任 務 書 3． ·畢業(yè)設計（論文）課題 果的要求〔包括圖`、實 硬件要求〕： 學ˇ查找 應的 料，通 論 計算，得出'優(yōu)的設計 案。 1、詳細 整的畢業(yè)設計說明書一份；?2萬 字以上，且要符合??要求； 2、 圖 一套；設計圖樣￡部用AutoCAD繪制。 3、外文?? 料 譯文 一套。 4． 要??文?： [1]胡仁喜.Pro/ENGINEER Wildfire.化學工業(yè)出 ?.2010年4月（ 一 ）. [2] ￡， . 機器人?術應用.￠? 出 ?.2012年1月（ ）. [3] ， ， . 動檢測與 …? 術.機 工業(yè)出 ?.2002年1月（ ）. [4] .機電一體化?術. 工業(yè)大學出 ?.2009年 12月（ 一 ）. [5] ， .液 傳動與?動?術. ￠大學出 ?.2006年1月（ 一 ）. [6] ￡?￡ˇ、￥?§．AutoCAD機 繪圖基currency1教程與實'. ￠大學出 ?.2007年8月（ 一 ）. [7]“??，￥?fi.可fl程控制器. 大學出 ?.2010年3月（ 一 ）. [8]– ?.電機與電?控制. 機 工業(yè)出 ?.2011年1月（ 一 ）. [9]PLC應用?術/ ? fl .- ￠：人· 電出 ?， 2010.10 [10]可fl程控制器應用?術（ ? ） fl：? ? [13]PLC電?控制與組?設計.”￠?fl .- ￠：?學出 ?，2003 [4]現(xiàn)?電?控制 PLC應用?術. ￠： ￠?…?‰大學出 ?，2000 [14] ?生 fl. 電?控制與可fl程控制器?術. ￠:化學工業(yè)出 ?.2004 [2] [15] ? .現(xiàn)?電? 可fl程控制?術. ￠: ￠?…?‰大學出 ?.2002 畢 業(yè) 設 計（論 文）任 務 書 5．·畢業(yè)設計（論文）課題工 度計 ： 2015.12.16-2016.1.10 發(fā)`任務書、開題， 畢業(yè)實′?? 2016.2.25-2.16.3.9 開題報ˉ、 ￠?文˙譯、論文大¨ 2016.3.19-2016.4.25 提?論文草 ，4月￠?￠期檢查 2016.4.26- 2016.5.6 提?論文? 2016.5.6-2016.5.13 準 ? 2016.5.13-2016.5.26 ? ， ???， ˇ改 '— 所在專業(yè)審查 ： 負責人： 2016 年 1 月 8 日 畢 業(yè) 設 計（論 文）開 題 報 告 設計（論文）題目：基于單片機的檔案庫房溫濕度監(jiān)控系統(tǒng) 學生姓名： 年 月 日 開題報告填寫要求 1．開題報告（含“文獻綜述”）作為畢業(yè)設計（論文）答辯委員會對學生答辯資格審查的依據(jù)材料之一。此 報告應在指導教師指導下，由學生在畢業(yè)設計（論文）工作前期內完成，經(jīng)指導教師簽署意見及所在專業(yè)審查 后生效； 2．開題報告內容必須用黑墨水筆工整書寫或按教務處統(tǒng)一設計的電子文檔標準格式打印，禁止打印在其它紙 上后剪貼，完成后應及時交 指導教師簽署意見； 3．“文獻綜述”應按論文的 成文， 書寫（或打?。┰?開題報告 一 目內，學生寫文獻綜述的 文獻應 于15 （ ）； 4． 年月日 日期的填寫，應 按 標GB/T 7408—94 據(jù) 交 格式 ?交 日期 時￠￡ ?￥?§currency1的要求，一'用“?? ?書寫。fi“2004年4月26日”或“2004-04-26”。 5 開題報告（文獻綜述）?fl 按–fl ??·書寫， ￠?1.5?。 畢 業(yè) 設 計（論文） 開 題 報 告 1．??畢業(yè)設計（論文）”題?…，‰據(jù)所查 的文獻資料，? `寫 于1000?′?的文獻綜述： 1.?目ˉ?˙¨ 意? 檔案? ??ˇ—的 ， 于 生資 。檔案庫房 的溫度 濕度 對檔案材料 的 度 ? 要的a 。對檔案庫房 的 的溫度 濕度 ? 及時的監(jiān) 控，?檔案 ???o 的 要 之一?？? 檔案庫房溫濕度的 ￥ ? ， ???，? 風 降濕相??的辦￥，?控? 庫房溫濕度的好辦￥，傳統(tǒng)的溫濕度測量 ￥ 過 工 檢測， 對 符?溫度 濕度要求的庫房 風 去濕 降溫 工作。費時 費力 效率低，且測試的溫度及濕度誤 差大，隨機性大。因此我們需要一種造價低廉 使用 便且測量準確的溫濕度測量儀。目前在在檔案房控?技 術上，主要 向? 機界面的 性 設計 網(wǎng)絡 控?技術 面，集中在更 便的操作， 種 選控? 式 上， ?用 機界面來使操作更容易。所 由單片機為核心的檔案房溫濕度控?系統(tǒng)開始更好地為大家服務。 2. 內外ˉ?現(xiàn)狀目前， 內大中型庫房在倉 管 中由于技術 資金上的原因， 僅限于只對溫度 監(jiān)測， 溫度超標時 強? 風 翻倉，即使fi此，處 及時或因設備 力條件 限仍會造成大量損失。 現(xiàn)庫房 藏物的升溫主要?由于濕度引起的，庫房 藏物 身的水分過高或連續(xù)的高濕天氣將導致 藏物新 陳代謝加快而放出熱量，放熱引起的升溫又使代謝 一步加劇 致發(fā)生霉 。這種惡性循 一旦形成?難 效的控?。因此，庫房在 溫度監(jiān)測的同時，必須 視空氣濕度的檢測， 利于提前? 效 施控?庫 房 藏物升溫而霉 。 文設計溫濕度控?系統(tǒng)由單片機為控?核心，??傳感器 訊 ?電子技術， 現(xiàn)了溫濕度的 效監(jiān)測，降低經(jīng)濟損失 勞動強度。‰據(jù)檔案房 藏物的需要，部分甚?完 的 ，使 為 造 的 的 動控?技術 成為主 。此時的 內 ? 完整的控?系統(tǒng)， 種傳感 器?集溫 據(jù)，監(jiān)控系統(tǒng) 時監(jiān)測 及控? 機 的動作， 好的 機界面使管 的操作過 形 而且 便。這種控?系統(tǒng)需要管 檔案 所要求 的目標 ，計 機‰據(jù)傳感器的 測量 設currency1的目標 ? ， currency1溫 因子的控?過 ，控?相應機 降溫 風 動作。計 機 動控?的溫 控?技術 現(xiàn)了監(jiān)管 動 ，勞動生 率o 提高。 過 檔案 設currency1目標 ， 動地 內 氣? 。我 大部分 主開發(fā)的大型現(xiàn)代 溫濕度監(jiān)管系統(tǒng)￠?引 的， 外設備￠ 于這種控? 式。 3. 文獻 [1]￡?￥.單片機原 及應用[M]， ?§currency1天currency1空大學出'“.2007.2 [2]???．傳感器原 fi設計 應用[M]，?§： fl 技大學出'“，2005：205-207． [3]–成?， ?新·， ?. 傳感器 動檢測技術[M] .?§：高 教?出'“，2006 [4]新型單片機AT89C2051及 其應用 ?[J] 1996年 04期 [5]金?. DS18B20 現(xiàn)高”度溫度測量[J]. ?…電子報, 2005, (2005-02-27) [6]‰ ?， `′.傳感器 ·處 [M].?§：電子工業(yè)出'“，1998 [7]?家?， ˉ?˙，¨ ?. 單片機 及應用技術[M] .?§：高 教?出'“，2006 [8]?? ．單片機原 及 ? 技術[M]，?§：?ˇ大學出'“，1996.7． [9]— . 動控?原 及其應用[M]，?§：高 教?出'“， 2004 [10] . 動檢測技術[M]，?§：機 工業(yè)出'“，2000 [11] ．單片機的C 應 用 設計[M]，?§：?§currency1空currency1天大學出'“，2003.11． [12] .單片機原 及應用[J]，?§： 高 教?出'“.2004 [13] ?.電動機的單片機控?.?§.?§currency1空currency1天大學出'“.2004 [14] ?.集成傳感器應用.中 電力出'“.2005.10 [15] a .單片機應用 ? 分 [M]，?§：?§currency1空 currency1天大學出'“.2003 畢 業(yè) 設 計（論文） 開 題 報 告 2． ”題要ˉ?或 的 題 ??用的ˉ? （??）： 1.工作o務分 件電 主要由單片機 DHT11溫濕度傳感器 12864 ?器 報?器及控?設備 5 部分 成。測溫濕度控?電 由溫濕度傳感器 設溫度 ? 報?電 成；用 需 設 ， 測量的溫濕度 符? 設的溫濕度標準時，由? 器發(fā)出報? ·， 動相應控?。 系統(tǒng)將檔案庫房的 溫濕度 據(jù)?集 發(fā)? ??處 器 分 處 ， 超出 設 后，控?系統(tǒng)發(fā)出??使?報系統(tǒng) 動，提 外界 工 。 主要 成 溫濕度?集部分，單片機控?部分 及?報系統(tǒng)。 2.畢業(yè)設計?目 施 及 度 1-2 ： 相 文獻資料及`寫畢業(yè)設計開題報告。 3-4 ：優(yōu) ??集電 設計 5-6 ： ˉ?文獻 設計 ??報及控?電 7-8 ： 一步 文獻，ˉ?系統(tǒng)軟件的設計， 主 模塊 溫濕度?集模塊 據(jù)轉 處 模塊 報?控?子 模塊 ?模塊及主 ??處 9-12 ：仿真分 新的電 ， 提 出? 的模型 工藝 。 13-14 ：`寫畢業(yè)設計報告，準備畢業(yè)答辯。 15 ： 畢業(yè)答辯。 畢 業(yè) 設 計（論文） 開 題 報 告 指導教師意見： 1．對“文獻綜述”的評 ： 文獻綜述符?畢業(yè)設計要求，對 ”題的 內外發(fā)展敘述 為詳細。 2．對 ”題的深度 廣度及工作量的意見 對設計（論文）?果的 測： ”題的深度 廣度及工作量符?畢業(yè)設計要求。相 過該生努力??順利完成設計。 3.?否同意開題：√ 同意 □ 同意 指導教師： 2016 年 03 月 08 日 所在專業(yè)審查意見： 同意 負責 ： 2016 年 04 月 05 日 畢 業(yè) 設 計（論 文）外 文 參 考 資 料 及 譯 文 譯文題目：The General Situation of AT89C51 AT89C51應用 學生姓名： 專 業(yè)： 所在學院： 指導教師： 職 稱： AT89C51的概況 The General Situation of AT89C51 Chapter 1 The application of AT89C51 Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Plaform Engineering department developed an object-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of thisenvironment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51. 1.1 Introduction The 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speedcalculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems,motor-control systems, printers, photocopiers, air conditioner control systems, disk drives,and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission criticalapplications such as an autopilot or anti-lock braking system, mistakes are financiallyprohibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions.This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully.Intel Chandler Platform Engineering group provides post silicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts.The type of the device and its application requirements determine which types of testing are performed on the device. 1.2 The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture,a full duple ser -ial port, on-chip oscillator and clock circuitry.In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters,serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscil –lator disabling all other chip functions until the next hardware reset. Figure 1-2-1Block Diagram 1-3Pin Description VCC Supply voltage. GND Ground. Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin cansink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data busduring accesses to external program and data memory. In this mode P0 has internalpullups.Port 0 also receives the code bytes during Flash programming,and outputs the codebytes during program verification. External pullups are required during programverification. Port 1：Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/so -urce four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification. Port 2：Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 outputbuffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they arepulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals durin Flash programming and verification. Port 3：Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 outputbuffers can sink/sou -rce four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special featuresof the AT89C51 as listed below: RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE/PROG：Address Latch Enable output pulse for latching the low byte of the address duringaccesses to external memory.This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency,and may be used for external timing or clocking purposes. Note, however, that one ALEpulse is skipped duri -ng each access to external DataMemory.If desired, ALE operationcan be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active onlyduring a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Settingthe ALE-disable bit has no effect if the microcontroller is in external execution mode. PSEN：Program Store Enable is the read strobe to external program memory. When theAT89C51 is executing code from external program memory, PSEN is activated twiceeach machine cycle, except that two PSEN activations are skipped during each access toexternal data memory. EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the deviceto fetch code from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched onreset.EA should be strapped to VCC for internal program executions. This pin alsreceives the 12-volt programming enable voltage (VPP) during Flash programming, forparts that require 12-volt VPP. XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operatingcircuit. XTAL2 ：Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifierwhich can be configured for use as an on-chip oscillator, as shown in Figure 1. Either aquartz crystal or ceramic resonator may be used. To drive the device from an externalclock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Power-down Mode In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode. 2 Programming Algorithm Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. 2.1Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Figure 2-1-1 Programming the Flash Figure 2-2-2 Verifying the Flash 2.2 Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed. 2.3 Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned areas follows. (030H) = 1EH indicates manufactured by Atmel (031H) = 51H indicates 89C51 (032H) = FFH indicates 12V programming (032H) = 05H indicates 5V programming 2.4 Programming Interface Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion. A microcomputer interface converts information between two forms. Outside the microcomputer the information handled by an electronic system exists as a physical signal, but within the program, it is represented numerically. The function of any interface can be broken down into a number of operations which modify the data in some way, so that the process of conversion between the external and internal forms is carried out in a number of steps. An analog-to-digital converter(ADC) is used to convert a continuously variable signal to a corresponding digital form which can take any one of a fixed number of possible binary values. If the output of the transducer does not vary continuously, no ADC is necessary. In this case the signal conditioning section must convert the incoming signal to a form which can be connected directly to the next part of the interface, the input/output section of the microcomputer itself. Output interfaces take a similar form, the obvious difference being that here the flow of information is in the opposite direction; it is passed from the program to the outside world. In this case the program may call an output subroutine which supervises the operation of the interface and performs the scaling numbers which may be needed for digital-to-analog converter(DAC). This subroutine passes information in turn to an output device which produces a corresponding electrical signal, which could be converted into analog form using a DAC. Finally the signal is conditioned(usually amplified) to a form suitable for operating an actuator. The signals used within microcomputer circuits are almost always too small to be connected directly to the outside world” and some kind of interface must be used to translate them to a more appropriate form. The design of section of interface circuits is one of the most important tasks facing the engineer wishing to apply microcomputers. We have seen that in microcomputers information is represented as discrete patterns of bits; this digital form is most useful when the microcomputer is to be connected to equipment which can only be switched on or off, where each bit might represent the state of a switch or actuator. To solve real-world problems, a microcontroller must have more than just a CPU, a program, and a data memory. In addition, it must contain hardware allowing the CPU to access information from the outside world. Once the CPU gathers information and processes the data, it must also be able to effect change on some portion of the outside world. These hardware devices, called peripherals, are the CPU’s window to the outside. The most basic form of peripheral available on microcontrollers is the general purpose I70 port. Each of the I/O pins can be used as either an input or an output. The function of each pin is determined by setting or clearing corresponding bits in a corresponding data direction register during the initialization stage of a program. Each output pin may be driven to either a logic one or a logic zero by using CPU instructions to pin may be viewed (or read.) by the CPU using program instructions. Some type of serial unit is included on microcontrollers to allow the CPU to communicate bit-serially with external devices. Using a bit serial format instead of bit-parallel format requires fewer I/O pins to perform the communication function, which makes it less expensive, but slower. Serial transmissions are performed either synchronously or asynchronously. 翻譯 AT89C51的概況 1 AT89C51應用 單片機廣泛應用于商業(yè)：諸如調制解調器，電動機控制系統(tǒng)，空調控制系統(tǒng)，汽車發(fā)動機和其他一些領域。這些單片機的高速處理速度和增強型外圍設備集合使得它們適合于這種高速事件應用場合。然而，這些關鍵應用領域也要求這些單片機高度可靠。健壯的測試環(huán)境和用于驗證這些無論在元部件層次還是系統(tǒng)級別的單片機的合適的工具環(huán)境保證了高可靠性和低市場風險。Intel 平臺工程部門開發(fā)了一種面向對象的用于驗證它的AT89C51 汽車單片機多線性測試環(huán)境。這種環(huán)境的目標不僅是為AT89C51 汽車單片機提供一種健壯測試環(huán)境，而且開發(fā)一種能夠容易擴展并重復用來驗證其他幾種將來的單片機。開發(fā)的這種環(huán)境連接了AT89C51。本文討論了這種測試環(huán)境的設計和原理，它的和各種硬件、軟件環(huán)境部件的交互性，以及如何使用AT89C51。 1.1 介紹 8 位AT89C51 CHMOS 工藝單片機被設計用于處理高速計算和快速輸入/輸出。MCS51 單片機典型的應用是高速事件控制系統(tǒng)。商業(yè)應用包括調制解調器，電動機控制系統(tǒng)，打印機，影印機，空調控制系統(tǒng)，磁盤驅動器和醫(yī)療設備。汽車工業(yè)把MCS51 單片機用于發(fā)動機控制系統(tǒng)，懸掛系統(tǒng)和反鎖制動系統(tǒng)。AT89C51 尤其很好適用于得益于它的處理速度和增強型片上外圍功能集，諸如：汽車動力控制，車輛動態(tài)懸掛，反鎖制動和穩(wěn)定性控制應用。由于這些決定性應用，市場需要一種可靠的具有低干擾潛伏響應的費用-效能控制器，服務大量時間和事件驅動的在實時應用需要的集成外圍的能力，具有在單一程序包中高出平均處理功率的中央處理器。擁有操作不可預測的設備的經(jīng)濟和法律風險是很高的。一旦進入市場，尤其任務決定性應用諸如自動駕駛儀或反鎖制動系統(tǒng)，錯誤將是財力上所禁止的。重新設計的費用可以高達500K 美元，如果產(chǎn)品族享有同樣內核或外圍設計缺陷的話，費用會更高。另外，部件的替代品領域是極其昂貴的，因為設備要用來把模塊典型地焊接成一個總體的價值比各個部件高幾倍。為了緩和這些問題，在最壞的環(huán)境和電壓條件下對這些單片機進行無論在部件級別還是系統(tǒng)級別上的綜合測試是必需的。Intel Chandler 平臺工程組提供了各種單片機和處理器的系統(tǒng)驗證。這種系統(tǒng)的驗證處理可以被分解為三個主要部分。系統(tǒng)的類型和應用需求決定了能夠在設備上執(zhí)行的測試類型。 1.2 AT89C51提供以下標準功能： 4k 字節(jié)FLASH 閃速存儲器，128 字節(jié)內部RAM，32 個I/O 口線，2 個16 位定時/計數(shù)器，一個5 向量兩級中斷結構，一個全雙工串行通信口，片內振蕩器及時鐘電路。同時，AT89C51 降至0Hz 的靜態(tài)邏輯操作，并支持兩種可選的節(jié)電工作模式?？臻e方式體制CPU 的工作，但允許RAM，定時/計數(shù)器，串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存RAM 中的內容，但振蕩器體制工作并禁止其他所有不見工作直到下一個硬件復位。 圖1-2-1 AT89C51 方框圖 1.3引腳功能說明 ·Vcc：電源電壓 ·GND：地 ·P0 口：P0 口是一組8 位漏極開路型雙向I/O 口，也即地址/數(shù)據(jù)總線復用。作為輸出口用時，每位能吸收電流的方式驅動8 個TTL 邏輯門電路，對端口寫“1”可作為高阻抗輸入端用。在訪問外部數(shù)據(jù)存儲器或程序存儲器時，這組口線分時轉換地址（低8 位）和數(shù)據(jù)總線復用，在訪問期間激活內部上拉電阻。在Flash 編程時，P0 口接受指令字節(jié)，而在程序校驗時，輸出指令字節(jié)，校驗時，要求外接上拉電阻。 ·P1 口：P1 是一個帶內部上拉電阻的8 位雙向I/O 口，P1 的輸出緩沖級可驅動（吸收或輸出電流）4 個TTL 邏輯門電路。對端口寫“1”，通過內部的上拉電阻把端口拉到高電平，此時可作輸入口。作為輸入口使用時，因為內部存在上拉電阻，某個引腳被外部信號拉低時會輸出一個電流（IIL）。Flash 編程和程序校驗期間，P1 接受低8 位地址。 ·P2 口：P2 是一個帶有內部上拉電阻的8 位雙向I/O 口，P2 的輸出緩沖級可驅動（吸收或輸出電流）4 個TTL 邏輯門電路。對端口寫“1”，通過內部的上拉電阻把端口拉到高電平，此時可作輸入口。作為輸入口使用時，因為內部存在上拉電阻，某個引腳被外部信號拉低時會輸出一個電流（IIL）。在訪問外部程序存儲器或16 位四肢的外部數(shù)據(jù)存儲器（例如執(zhí)行MOVX @DPTR指令）時，P2 口送出高8 位地址數(shù)據(jù)，在訪問8 位地址的外部數(shù)據(jù)存儲器（例如執(zhí)行MOVX @ RI 指令）時，P2 口線上的內容（也即特殊功能寄存器（SFR）區(qū)中R2 寄存器的內容），在整個訪問期間不改變。Flash 編程和程序校驗時，P2 也接收高位地址和其他控制信號。 ·P3 口：P3 是一個帶有內部上拉電阻的8 位雙向I/O 口，P3 的輸出緩沖級可驅動（吸收或輸出電流）4 個TTL 邏輯門電路。對端口寫“1”，通過內部的上拉電阻把端口拉到高電平，此時可作輸入口。作為輸入口使用時，因為內部存在上拉電阻，某個引腳被外部信號拉低時會輸出一個電流（IIL）。P3 口還接收一些用于Flash 閃速存儲器編程和程序校驗的控制信號。 ·RST：復位輸入。當振蕩器工作時，RST 引腳出現(xiàn)兩個機器周期以上高電平將使單片機復位。 ·ALE/PROG：當訪問外部程序存儲器或數(shù)據(jù)存儲器時，ALE（地址鎖存允許）輸出脈沖用于鎖存地址的低8 位字節(jié)。即使不訪問外部存儲器，ALE 仍以時鐘振蕩頻率的1/6 輸出固定的正脈沖信號，因此它可對外輸出時鐘或用于定時目的。要注意的是，每當訪問外部數(shù)據(jù)存儲器時將跳過一個ALE 脈沖。對Flash 存儲器編程期間，該引腳還用于輸入編程脈沖（PROG）。如有必要，可通過對特殊功能寄存器（SFR）區(qū)中的8EH 單元D0 位置位，可禁止ALE 操作。該位置位后，只有一條MOVX 和MOVC 指令ALE 才會被激活。此外，該引腳會被微弱拉高，單片機執(zhí)行外部程序時，應設置ALE 無效。 ·PSEN：程序存儲允許輸出是外部程序存儲器的讀選通型號，當89C51 由外部存儲器取指令（或數(shù)據(jù)）時，每個機器周期兩次PSEN 有效，即輸出兩個脈沖。在此期間，當訪問外部數(shù)據(jù)存儲器，這兩次有效的PSEN 信號不出現(xiàn)。 ·EA/VPP