汽車尾燈控制電路設(shè)計資料,汽車,尾燈,控制電路,設(shè)計,資料 天津工程師范學(xué)院 畢業(yè)設(shè)計（論文）前期檢查表 填表時間：2005年11月28日 專業(yè)班級 電氣041 學(xué)生姓名 盧遙 指導(dǎo)教師 李杰 職稱 教授 課題名稱 汽車尾燈控制電路設(shè)計 選 題 方 面 是否屬專業(yè)內(nèi)容 屬于 結(jié)合實際程度 緊密結(jié)合實際 先進性可行性 可行性強 難易程度 適當(dāng) 任 務(wù) 書 填 寫 規(guī)范程度 規(guī)范 主要技術(shù)指標是否具體 具體 工作量大小 適中 圖紙及實物要求具體程度 符合要求 參考文獻填寫規(guī)范程度 規(guī)范 開題報告或 方案論證 可行性 是 必要性 是 先進性 是 經(jīng)濟技術(shù)分析 是 有 何 建 議 教研室主任簽字： 系主任簽字： 1 引言 在日新月異的21世紀里，電子產(chǎn)品得到了迅速發(fā)展。許多電器設(shè)備都趨于人性化、智能化，這些電器設(shè)備大部分都含有CPU控制器或者是單片機。單片機以其高可靠性、高性價比、低電壓、低功耗等一系列優(yōu)點，近幾年得到迅猛發(fā)展和大范圍推廣，廣泛應(yīng)用于工業(yè)控制系統(tǒng)、通訊設(shè)備、日常消費類產(chǎn)品和玩具等。并且已經(jīng)深入到工業(yè)生產(chǎn)的各個環(huán)節(jié)以及人民生活的各個方面，如車間流水線控制、自動化系統(tǒng)等、智能型家用電器（冰箱、空調(diào)、彩電）等。用單片機來控制的小型電器產(chǎn)品具有便攜實用，操作簡單的特點。 本文設(shè)計的汽車尾燈控制電路屬于小型智能電子產(chǎn)品。利用單片機進行控制，實時時鐘芯片進行記時，外加掉電存儲電路和顯示電路。此設(shè)計具有相當(dāng)重要的現(xiàn)實意義和實用價值。 2 系統(tǒng)概述 本設(shè)計以AT89S52單片機為核心，構(gòu)成單片機控制電路，完成對它們的自動調(diào)整和掉電保護。人機接口由四個按鍵來實現(xiàn)，用這四個按鍵對汽車左轉(zhuǎn)，右轉(zhuǎn)，停車和檢測進行控制。。軟件控制程序?qū)崿F(xiàn)所有的功能。整機電路使用+5V穩(wěn)壓電源，可穩(wěn)定工作。系統(tǒng)框圖如圖2-1所示，其軟硬件設(shè)計簡單，可廣泛應(yīng)用于長時間工作的系統(tǒng)中。 人機接口 顯示電路 軟件控制程序 電源電路 單片機控制電路 圖2-1 系統(tǒng)框圖 3 方案選擇 由于汽車尾燈控制電路的種類比較多，因此方案選擇在設(shè)計中是至關(guān)重要的。正確地選擇方案可以減小開發(fā)難度，縮短開發(fā)周期，降低成本，更快地將產(chǎn)品推向市場。 3.1 方案1——基于AT89S52單片機的汽車尾燈控制電路設(shè)計 直接用AT89S52單片機來實現(xiàn)汽車尾燈控制電路設(shè)計。AT89S52是一種帶8K字節(jié)閃爍可編程可擦除只讀存儲器的低電壓，高性能CMOS 8位微處理器，俗稱單片機。單片機的可擦除只讀存儲器可以反復(fù)擦寫1000余次。由于將多功能8位CPU和閃爍存儲器組合在單個芯片中，ATMEL的AT89S52是一種高效微控制器，為很多嵌入式控制系統(tǒng)提供了一種靈活性高且價廉的方案。 用單片機來實現(xiàn)汽車尾燈控制電路設(shè)計，無須外接其他芯片，充分利用了單片機的資源。 3.2 方案2——基于電子元件的汽車尾燈控制電路設(shè)計 用電子元件接的汽車尾燈控制電路，電路復(fù)雜，接點較多，電路穩(wěn)定性差。 汽車左右和剎車仿真電路 開關(guān)控制電路 譯碼電路74138 顯示驅(qū)動電路 記數(shù)電路74161 R1R2R3 L1L2L3 脈沖產(chǎn)生電路555 汽車尾燈控制電路設(shè)計總體框圖 4 系統(tǒng)硬件電路的設(shè)計 按照系統(tǒng)設(shè)計功能的要求，初步確定設(shè)計系統(tǒng)由主控模塊、鍵盤接口模塊、顯示模塊共3個模塊組成，電路系統(tǒng)構(gòu)成框圖如圖4-1所示。主控芯片使用52系列AT89S52單片機， （89S52） 主控模塊 時鐘電路 鍵掃描電路 晶體管顯示 存儲電路 圖4-1 汽車尾燈控制電路系統(tǒng)構(gòu)成框圖 4.1 系統(tǒng)核心部分——閃電存儲型器件AT89S52 4.1.1 AT89S52具有下列主要性能[5]： ·8KB可改編程序Flash存儲器（可經(jīng)受1000次的寫入/擦除周期） ·全靜態(tài)工作：0Hz～24MHz ·三級程序存儲器保密 ·128×8字節(jié)內(nèi)部RAM ·32條可編程I/O線 ·2個16位定時器/計數(shù)器 ·6個中斷源 ·可編程串行通道 ·片內(nèi)時鐘振蕩器 4.1.2 AT89S52的引腳及功能 AT89S52單片機的管腳說明如圖4-2所示。 圖4-2 AT89S52的管腳 (1) 主要電源引腳 ①VCC 電源端 ②GND 接地端 (2) 外接晶體引腳XTAL1和XTAL2 ①XTAL1 接外部晶體的一個引腳。在單片機內(nèi)部，它是構(gòu)成片內(nèi)振蕩器的反相放大器的輸入端。當(dāng)采用外部振蕩器時，該引腳接收振蕩器的信號，既把此信號直接接到內(nèi)部時鐘發(fā)生器的輸入端。 ②XTAL2 接外部晶體的另一個引腳。在單片機內(nèi)部，它是上述振蕩器的反相放大器的輸出端。采用外部振蕩器時，此引腳應(yīng)懸浮不連接。 (3) 控制或與其它電源復(fù)用引腳RST、ALE//PROG、/PSEN和/EA/VPP ①RST 復(fù)位輸入端。 當(dāng)振蕩器運行時，在該引腳上出現(xiàn)兩個機器周期的高電平將使單片機復(fù)位。 ②ALE//PROG 當(dāng)訪問外部存儲器時，ALE（地址鎖存允許）的輸出用于鎖存地址的低位字節(jié)。即使不訪問外部存儲器，ALE端仍以不變的頻率（此頻率為振蕩器頻率的1/6）周期性地出現(xiàn)正脈沖信號。因此，它可用作對外輸出的時鐘，或用于定時目的。然而要注意的是：每當(dāng)訪問外部數(shù)據(jù)存儲器時，將跳過一個ALE脈沖。在對Flash存儲器編程期間，該引腳還用于輸入編程脈沖（/PROG）[6]。 ③/PSEN 程序存儲允許（/PSEN）輸出是外部程序存儲器的讀選通信號。當(dāng)AT89S52/LV52由外部程序存儲器取指令（或常數(shù)）時，每個機器周期兩次/PSEN有效（既輸出2個脈沖）。但在此期間內(nèi)，每當(dāng)訪問外部數(shù)據(jù)存儲器時，這兩次有效的/PSEN信號將不出現(xiàn)。 ④/EA/VPP 外部訪問允許端。要使CPU只訪問外部程序存儲器（地址為0000H～FFFFH），則/EA端必須保持低電平（接到GND端）。當(dāng)/EA端保持高電平（接VSS端）時，CPU則執(zhí)行內(nèi)部程序存儲器中的程序。 (4) 輸入/輸出引腳 P0.0～ P0.7、P1.0～P1.7、P2.0～ P2.7 和P3.0～P3.7 ①P0端口（P0.0～ P0.7） P0是一個8位漏極開路型雙向I/O端口。作為輸出口用時，每位能以吸收電流的方式驅(qū)動8個TTL輸入，對端口寫1時，又可作高阻抗輸入端用。 ②P1端口（P1.0～ P1.7） P1是一個帶有內(nèi)部上拉電阻的8位雙向I/O端口。P1的輸出緩沖器可驅(qū)動（吸收或輸出電流方式）4個TTL輸入。對端口寫1時，通過內(nèi)部的上拉電阻把端口拉到高電位，這時可用作輸入口。作輸入口時，因為有內(nèi)部的上拉電阻，那些被外部信號拉低的引腳會輸出一個電流。 ③P2端口 （P2.0～P2.7） P2是一個帶有內(nèi)部上拉電阻的8位雙向I/O端口。P2的輸出緩沖器可驅(qū)動（吸收或輸出電流方式）4個TTL輸入。對端口寫1時，通過內(nèi)部的上拉電阻把端口拉到高電位，這時可用作輸入口。P2作輸入口使用時，因為有內(nèi)部的上拉電阻，那些被外部信號拉低的引腳會輸出一個電流。 ④P3端口（P3.0～P3.7） P3口管腳是8個帶內(nèi)部上拉電阻的雙向I/O口，可接收輸出4個TTL門電流。當(dāng)P3口寫入“1”后，它們被內(nèi)部上拉為高電平，并用作輸入。作為輸入，由于外部下拉為低電平，P3口將輸出電流，這是由于上拉的緣故。 P3口也可作為AT89S52的一些特殊功能，這些特殊功能見表4-1[7]。 表4-1 P3端口的特殊功能 端口引腳 兼 用 功 能 P3.0 RXD （串行輸入口） P3.1 TXD （串行輸出口） P3.2 /INT0 （外部中斷0） P3.3 /INT1 （外部中斷1） P3.4 T0 （ 定時器0的外部輸入） P3.5 T1 （定時器1的外部輸入） P3.6 /WR （外部數(shù)據(jù)存儲器寫選通） P3.7 /RD （外部數(shù)據(jù)存儲器讀選通） 4.5 鍵盤電路 本設(shè)計共采用按鍵4個，分別與單片機的P2.0、P2.1、P2.2、P2.3口相連，分別對應(yīng)汽車左轉(zhuǎn)，汽車右轉(zhuǎn)，剎車和檢測的功能。 7 結(jié)論 本設(shè)計硬件電路較簡單，所用器件較少，電路中使用了AT89S52單片主要芯片,實現(xiàn)了預(yù)計功能。 在對芯片的管腳功能和用法有充分的了解后，根據(jù)設(shè)計要求設(shè)計硬件電路，然后通過軟件編程，用按鍵進行控制，用發(fā)光二極管進行顯示。 汽車尾燈控制電路可以正常顯示汽車的左轉(zhuǎn)，右轉(zhuǎn)，停車和檢測功能，基本完成了預(yù)期要實現(xiàn)的目標。 參考文獻 1．康華光主編，電子技術(shù)基礎(chǔ)(數(shù)字部分)，高等教育出版社 2．標準集成電路數(shù)據(jù)手冊TTL電路，電子工業(yè)出版社 致 謝 不知不覺，六周的畢業(yè)設(shè)計結(jié)束了。我的畢業(yè)論文已整理完畢，電路調(diào)試進展良好。畢業(yè)設(shè)計的完成意味著我的大學(xué)學(xué)習(xí)生活即將結(jié)束，從此我將進入一個新的人生旅途、開始一段嶄新的生活——工作。在此，我衷心地感謝所有在我做畢業(yè)設(shè)計期間幫助過我的人。 首先我要感謝我的指導(dǎo)老師李杰的大力幫助和支持。在整個設(shè)計過程當(dāng)中，李老師在大局上指導(dǎo)我畢業(yè)設(shè)計的每一進程，還在百忙中抽空為我答疑解難，幫我分析講解畢業(yè)設(shè)計中所遇到的問題。不僅如此，李老師還無私的給我提供了豐富的學(xué)習(xí)資源和良好的學(xué)習(xí)環(huán)境，為我的畢業(yè)設(shè)計帶來了很大方便。同時在我完成畢業(yè)設(shè)計的過程中提供了很多指導(dǎo)性的意見，使我受益匪淺。另外，李老師淵博的學(xué)識、嚴謹?shù)闹螌W(xué)態(tài)度和為人給了我很大的教育，這些將使我終身受益。在此，我衷心感謝李老師給予我的幫助和教育。 此外，我還要感謝夏九和李國華同學(xué)給予我的無私的幫助，他們在程序編寫和調(diào)試過程中給予了我莫大的幫助。在此，我真誠地感謝他們。 最后，我要感謝我的母?！旖蚬こ處煼秾W(xué)院，在校期間，這里給我留下了美好的回憶。特別是在我即將踏上工作崗位的同時，畢業(yè)設(shè)計整個過程給了我這樣一個鍛煉的機會，使我加深了對以前知識的理解和鞏固，拓寬了知識面，也提高了我對所學(xué)知識的綜合應(yīng)用能力。我要對母校說：母校有我三五載，我愛母校一萬年。祝愿母校的將來更美好！ 附錄1：汽車尾燈控制電路設(shè)計電路原理圖 附錄2 主程序 org 00h ajmp start ORG 001BH ;定時器T1中斷程序入口 LJMP time1 ;跳至INTT1執(zhí)行 org 0030h start: mov TMOD,#10h mov IE,#88h MOV TH1,#00h MOV TL1,#00h mov r7,#03h; setb TR1 turn: jnb p2.0,is_key jnb p2.1,is_key jnb p2.2,is_key jnb p2.3,is_key orl p1,#0ffh; is_key : jb p2.3,no_check; anl p1,#0c0h; jmp turn no_check: jmp turn time1: push acc mov TH1,#010h mov TL1,#00h jb p2.0,left djnz r7,return mov r7,#3 xrl p1,#3fh left: jb p2.1,right dec r7; cjne r7,#6,next1; mov p1,#0fbh next1: cjne r7,#3,next2; mov p1,#0fdh; next2: cjne r7,#0,right; mov p1,#0feh mov r7,#9; right: jb p2.2,return dec r7; cjne r7,#6,next11; mov p1,#0f7h next11: cjne r7,#3,next21; mov p1,#0efh; next21: cjne r7,#0,return; mov p1,#0dfh mov r7,#9; return: pop acc reti end 英文資料及中文翻譯 6 TRANSMISSIONS OF DIGITAL DATA: INTERFACES AND MODEMS (From Introduction to Data Communications and Net Working, Behrouz Forouzan) Once we have encoder our information into a format that can be transmitted, the next step is to investigate the transmission process itself. Information-processing equipment such as PCs generate encoded signals but ordinarily require assistance to transmit those signals over a communication link. For example, a PC generates a digital signal but needs an additional device to modulate a carrier frequency before it is sent over a telephone line. How do we relay encoded data from the generating device to the next device in the process? The answer is a bundle of wires, a sort of mini communication link, called an interface. Because an interface links two devices not necessarily made by the same manufacturer, its characteristics must be defined and standards must be established. Characteristics of an interface include its mechanical specifications (how many wires are used to transport the signal); its electrical specifications (the frequency, amplitude, and phase of the expected signal); and its functional specifications (if multiple wires are used, what does each one do?). These characteristics are all described by several popular standards and are incorporated in the physical layer of the OSI model. 6.1 DIGITAL DATA TRANSMISSION Of primary concern when considering the transmission of data from one device to another is the wiring. And of primary concern when considering the wiring is the data stream. Do we send one bit at a time, or do we group bits into larger groups and, if so, how? The transmission of binary data across a link can be accomplished either in parallel mode or serial mode. In parallel mode, multiple bits are sent with each clock pulse. In serial mode, one bit is sent with each clock pulse. While there is only one way to send parallel data, there are two subclasses of serial transmission: synchronous and asynchronous (see Figure 6-1). Parallel Transmission Binary data, consisting of 1s and 0s, may be organized into groups of n bits each. Computers produce and consume data in groups of bits much as we conceive of and use spoken language in the form of words rather than letters. By grouping, we can send data n bits at a time instead of one. This is called parallel transmission. Data transmission Parallel Serial Synchronous Asynchronous Figure 6-1　Data transmission The mechanism for parallel transmission is a conceptually simple one: use n wires to send n bits at one time. That way each bit has its own wire, and all n bits of one group can be transmitted with each clock pulse from one device to another. Figure 6-2 shows how parallel transmission works for n=8.Typically the eight wires are bundled in a cable with a connector at each end. Sender Receiver We need eight lines s 8 bit synchronously Figure 6-2　Parallel transmission The advantage of parallel transmission is speed. All else being equal, parallel transmission can increase the transfer speed by a factor of n over serial transmission. But there is a significant disadvantage: cost. Parallel transmission requires n communication lines (wires in the example) just to transmit the data stream. Because this is expensive, parallel transmission is usually limited to short distances, up to a maximum of say 25 feet. Serial Transmission In serial transmission one bit follows another, so we need only one communication channel rather than n to transmit data between two communicating devices . The advantage of serial over parallel transmission is that with only one communication channel, serial transmission reduces the cost of transmission over parallel by roughly a factor of n. Since communication within devices is parallel, conversion devices are required at the interface between the sender and the line (parallel-to-parallel). Serial transmission occurs in one of two ways: asynchronous or synchronous. Asynchronous Transmission Asynchronous transmission is so named because the timing of a signal is unimportant. Instead, information is received and translated by agreed-upon patterns. As long as those patterns are followed, the receiving device can retrieve the information without regard to the rhythm in which it is sent. Patterns are based on grouping the bit stream into bytes. Each group, usually eight bits, is sent along the link as a unit. The sending system handles each group independently, relaying it to the link whenever ready, without regard to a timer. Without a synchronizing pulse, the receiver cannot use timing to predict when the next group will arrive. To alert the receiver to the arrival of a new group, therefore, an extra bit is added to the beginning of each byte. This bit, usually a 0, is called the start bit. To let the receiver know that the byte is finished, one or more additional bits are appended to the end of the byte. These bits, usually 1s, are called stop bits. By this method, each byte is increased in size to at least 10 bits, of which 8 are information and 2 or more are signals to the receiver. In addition, the transmission of each byte may then be followed by a gap of varying duration. This gap can be represented either by an idle channel or by a stream of additional stop bits. In asynchronous transmission we send one start bit (0) at the beginning and one or more stop bits (1s) at the end of each byte. There may be a gap between each byte. The start and stop bits and the gap alert the receiver to the beginning and end of each byte and allow it to synchronize with the data stream. This mechanism is called asynchronous because, at the byte level, sender and receiver do not have to be synchronized. But within each byte, the receiver must still be synchronized with the incoming bit stream. This is, some synchronization is required, but only for the duration of a single byte. The receiving device resynchronizes at the onset of each new byte. When the receiver detects a start bit, it sets a timer and begins counting bits as they come in. after n bits the receiver looks for a stop bit. As soon as it detects the stop bit, it ignores any received pulses until it detects the next start bit. Asynchronous here means “asynchronous at the byte level,” but the bits are still synchronized; their durations are the same. The addition of stop and start bits and the insertion of gaps into the bit stream make asynchronous transmission slower than forms of transmission that can operate without the addition of control information. But it is cheap and effective, two advantages that make it an attractive choice for situations like low-speed communication. For example, the connection of a terminal to a computer is a natural application for asynchronous transmission. A user types only one character at a time, types extremely slowly in data processing terms, and leaves unpredictable gaps of time between each character. Synchronous Transmission In synchronous transmission, the bit stream is combined into longer “frames,” which may contain multiple bytes. Each byte, however, is introduced onto the transmission link without a gap between it and the next one. It is left to the receiver to separate the bit stream into bytes for decoding purposes. In other words, data are transmitted as an unbroken string of 1s and 0s, and the receiver separates that string into the bytes, or characters, it needs to reconstruct the information. In synchronous transmission we send bits one after another without start/stop bits or gaps. It is the responsibility of the receiver to group the bits. Without gaps and start/stop bits, there is no built-in mechanism to help the receiving device adjust its bit synchronization in midstream. Timing becomes very important, therefore, because the accuracy of the received information is completely dependent on the ability of the receiving device to keep an accurate count of the bits as they come in. The advantage of synchronous transmission is speed. With no extra bits or gaps to introduce at the sending end and remove at the receiving end and, by extension, with fewer bits to move across the link, synchronous transmission is faster than asynchronous transmission is faster than asynchronous transmission. For this reason, it is more useful for high-speed applications like the transmission of data from one computer to another. Byte synchronization is accomplished in the data link layer. 6.2 DTE-DCE INTERFAC At this point we must clarify two terms important to computer networking: data terminal equipment (DTE). There are usually four basic functional units involved in the communication of data: a DTE and DCE on one end and a DCE and DTE on the other end. The DTE generates the data and passes them, along with any necessary control characters, to a DCE. The DCE does the job of converting the signal to a format appropriate to the transmission medium and introducing it onto the network link. When the signal arrives at the receiving end, this process is reversed. Data Terminal Equipment (DTE) Data terminal equipment (DTE) includes any unit that functions either as a source of or as a destination for binary digital data. At the physical layer, if can be a terminal, microcomputer, computer, printer, fax machine, or any other device that generates or consumes digital data. DTEs do not often communicate directly with one another, they generate and consume information but need an intermediary to be able to communicate. Think of a DTE as operating the way your brain does when you talk. Let’s say you have an idea that you want to communicate to a friend. Your brain creates the idea but cannot transmit that idea to your friend’s brain by itself. Unfortunately or fortunately, we are not a species of mind readers. Instead, your brain passes the idea to your vocal chords and mouth, which convert it to sound waves that can travel through the air or over a telephone line to your friend’s ear and from there to his or her brain, where it is converted back into information. In this model, your brain and your friend’s brain are DTEs. Your vocal chords and mouth are your DCE. His or her ear is also a DCE. The air or telephone wire is your transmission medium. A DTE is any device that is a source of or destination for binary digital data. Data Circuit-Terminating Equipment (DCE) Data circuit-terminating equipment (DCE) includes any functional unit that transmits or receives data in the form of an analog or digital signal through a network. At the physical layer, a DCE takes data generated by a DTE, converts them to an appropriate signal, and then introduces the signal onto the telecommunication link. Commonly used DCEs at this layer include modems . In any network, a DTE generates digital data and passes it to a DCE; the DCE converts the data to a form acceptable to the transmission medium and sends the converted signal to another DCE on the network. The second DCE takes the signal off the line, converts it to a form usable by its DTE, and delivers it. To make this communication possible, both the sending and receiving DCEs must use the same encoding method, much the way that if you want to communicate to someone who understands only Japanese, you must speak Japanese. The two DTEs do not need to be coordinated with each other, but each of them must be coordinated with its own DCE and the DCEs must be coordinated so that data translation occurs without loss of integrity. A DCE is any device that transmits or receives data in the form of an analog or digital signal through a network. 6 數(shù)字數(shù)據(jù)傳輸：接口和調(diào)制解調(diào)器 （選自?數(shù)據(jù)通信與網(wǎng)絡(luò)?， Behrouz Forouzan著） 我們將信息編碼成可以傳輸?shù)母袷?，下一步就是探討傳輸過程了。信息處理設(shè)備如個人計算機能生成編碼信號，通常還需要其它設(shè)備協(xié)助才能將這些信號在通信鏈路上傳輸。例如一臺PC機產(chǎn)生數(shù)字信號，在將信號通過電話線發(fā)送之前，還需要一臺附加設(shè)備來調(diào)制載波頻率。在這過程中，我們怎樣才能把數(shù)據(jù)從產(chǎn)生它的設(shè)備傳送到下一個設(shè)備呢？解決辦法是使用一捆導(dǎo)線，成為一種為通信鏈路，或叫接口。 因為接口連接的兩個設(shè)備有可能不是一個廠家生產(chǎn)的，所以必須規(guī)定接口的特性并建立標準。接口特性包括機械規(guī)范（使用多少條導(dǎo)線來傳輸信號）、電氣規(guī)范（預(yù)期信號的頻率、振幅和相位）以及功能規(guī)范（如果使用多條導(dǎo)線，每條導(dǎo)線的功能是什么？）。這些特性在一些常用標準中都有描述并且被集成到了OSI7層模型的物理層中。 6.1數(shù)字數(shù)據(jù)傳輸 數(shù)據(jù)傳輸 并行傳輸 串行傳輸 同步傳輸 異步傳輸 從一個設(shè)備向另一個設(shè)備發(fā)送數(shù)據(jù)主要考慮的是配線方式。對于配線問題主要考慮的因素是數(shù)據(jù)流。我們是否一次只發(fā)送一個比特，或是將比特成組發(fā)送以及如何成組？通過鏈路傳輸二進制數(shù)據(jù)可以采用并行模式或串行模式。在并行模式中，在每個時鐘脈沖到來時多個比特被同時發(fā)送。在串行模式中，每個時鐘脈沖只發(fā)送一個比特。盡管只有一種發(fā)送并行數(shù)據(jù)的方法，串行傳輸卻有兩個子類：同步方式和異步方式（參見圖6-1）。 圖6-1 數(shù)據(jù)傳輸 6.1.1 并行傳輸 由0和1組成的二進制值可以組成n比特的位組。計算機使用和生成以比特為單位的數(shù)據(jù)，就像我們在英語會話時用詞而不是一個個的字母來交流一樣。通過分組，我們可以一次發(fā)送n個比特而不是一個比特。這稱為并行傳輸。 從概念上說，并行傳輸?shù)臋C制很簡單：一次使用n條導(dǎo)線來傳輸n個比特。這種方式下，每個比特都使用專門的線路，而一組中的n個比特就可以在每個時鐘脈沖從一個設(shè)備傳輸?shù)搅硪粋€設(shè)備。圖6-2顯示了n=8時并行傳輸?shù)墓ぷ鳡顩r。通常八根導(dǎo)線被捆成一根電纜，兩端都有連接頭。 8個比特一起發(fā)送 接收方 需要8條線 s 發(fā)送方 圖6-2 并行傳輸 并行傳輸?shù)膬?yōu)勢在于速度。當(dāng)其它因素相同時，并行傳輸將比串行傳輸?shù)乃俣瓤靚倍，但同時也存在一個嚴重缺點：費用高。為進行數(shù)據(jù)傳輸，并行傳輸需要n條通信線路（本例中是導(dǎo)線）。因為如此昂貴，所以并行傳輸通常被限制在最長25英尺的距離內(nèi)。 6.1.2 串行傳輸 在串行傳輸中，比特是一個一個一次發(fā)送的，因此在兩個通信設(shè)備之間傳輸數(shù)據(jù)只要一條通信通道，而不是n條。 串行傳輸相對于并行傳輸?shù)膬?yōu)點是：因為只需要一條通信信道，串行傳輸?shù)牡馁M用大約只是并行傳輸?shù)膎分之一。 因為在設(shè)備內(nèi)部的傳輸是并行的，所以在發(fā)送端和線路之間以及接收端和線路之間的接口上，都需要有轉(zhuǎn)換器（前者是并/串轉(zhuǎn)換，后者是串/并轉(zhuǎn)換）。 串行傳輸以兩種方式進行：同步方式和異步方式。 (1) 異步傳輸 如果在傳輸中信號的時序并不重要，我們就將這種傳輸稱為異步傳輸。它與同步方式不同的事，信息是以一種約定的模式來被接收和翻譯的。只要遵照約定模式，接收設(shè)備就可以以不理會信息發(fā)送的節(jié)奏而能正確獲取信息。約定模式是基于將比特組成字節(jié)。每一組比特（通常為八個）作為一個單位通過鏈路傳輸。發(fā)送端系統(tǒng)單獨處理每個組，每處理完一個組就將其轉(zhuǎn)發(fā)到鏈路上，并不理會時鐘信號。 因為沒有同步脈沖，接收方步可能通過及是方式來預(yù)測下一組比特何時到達。因而，為了通知接收方有新的比特組到達，在每字節(jié)的開頭都要附加一個比特。這個比特，通常是0，被稱為起始位。為了讓接收方知道一個字節(jié)已經(jīng)結(jié)束，在每字節(jié)尾部還要加上一個或多個比特。這些比特，通常是1，被稱為停止位。利用以上的方法，每字節(jié)的大小至少增加到了10個比特，其中有8比特的信息在加上2個或更多的提示接收方的信號。另外，每發(fā)送完一個字節(jié)，可能還要跟上一段可變長的時間間隙。這段間隙或者通過信道控閑狀態(tài)代表，或者通過附加的停止比特流代表。 在異步傳輸中，需要在每字節(jié)開始時發(fā)送一個起始位（0），然后在結(jié)束時發(fā)送一個或多個停止位（1）。在字節(jié)之間可以插入間隙。 起始位、停止位和間隙將一個字節(jié)的起始和終止提示給接收放，使得接收方可以根據(jù)數(shù)據(jù)流進行同步。因為在字節(jié)這一級別，發(fā)送方和接收方不需要進行同步，所以這種傳輸方式稱為異步傳輸。但是在每一字節(jié)內(nèi)，接受方仍要根據(jù)比特流來進行同步。也就是說，一定程度上的同步還是存在的，但僅僅局限在一個字節(jié)的時間內(nèi)。在每一個字節(jié)的開始，接收端設(shè)備就進行重同步。當(dāng)接收方檢測到一個起始位后，就啟動一個時鐘，并隨著到來的比特開始記數(shù)。在接受完n個比特后，接受方就等待停止位到達。當(dāng)檢測到停止位到達時，接受方在下一個起始位到達前忽略接收的所有信號。 異步傳輸意味著在字節(jié)級別以異步方式進行，但是每比特仍需要同步，他們的時延是一致的。 相對于不需要控制信息的傳輸方式，異步傳輸由于加入了起始位、停止位以及比特流間插入了間隙而顯得慢一些。但是這種方式既便宜又有效，這兩大優(yōu)點使得在低速通信這一類情形下異步傳輸方式顯得很有吸引力。例如，一臺終端到計算機的連接很自然就是一種異步傳輸?shù)膽?yīng)用實例。用戶一次只敲一個字符，這在數(shù)據(jù)通信領(lǐng)域內(nèi)是十分低速的，同時還在字符之間引入了不可預(yù)計長短的時間間隙。 (2) 同步傳輸 在同步傳輸中，比特流被組裝成更長的“幀”，一幀包含有許多個字節(jié)。與異步方式不同的是，引入幀內(nèi)的字節(jié)與字節(jié)之間沒有間隙，需要接收方在解碼時將比特流分解成字節(jié)。也就是說，數(shù)據(jù)被當(dāng)作不簡短的0、1比特流傳輸，而接收方來將比特流分割成重建信息所需的一個個字節(jié)。 在同步傳輸中，不插入起始/停止比特或間隙就將比特依次發(fā)送出去，完全有接收方負責(zé)重組比特。 因為沒有間隙和起始/停止位，就沒有勒比特流內(nèi)部的同步機制可以幫助接收端設(shè)備在處理比特流時調(diào)整比特同步。因為所接收數(shù)據(jù)的準備性完全依賴于接收端設(shè)備根據(jù)比特到達進行精確的比特計數(shù)的能力，所以時序變得十分重要。 同步傳輸?shù)膬?yōu)點是速度快。因為在發(fā)送端不需要插入附加的比特和間隙，再接收端也不需要去掉這些比特和間隙，因而在傳輸方式在類似計算幾件數(shù)據(jù)串是這樣的高速應(yīng)用中更有效。字節(jié)同步在數(shù)據(jù)鏈路層實現(xiàn)。 6.2 數(shù)據(jù)終端設(shè)備和數(shù)據(jù)電路中接設(shè)備接口 在這里必須首先分清計算機網(wǎng)絡(luò)中的兩個重要概念：數(shù)據(jù)終端設(shè)備（DTE）和數(shù)據(jù)電路終結(jié)設(shè)備（DCE）。在數(shù)據(jù)通信中經(jīng)常涉及到四個基本功能單元：兩端各有一個DTE和一個DCE。數(shù)據(jù)終端設(shè)備（DCE）將信號轉(zhuǎn)換成適用于傳輸介質(zhì)的形式并將它發(fā)送到網(wǎng)絡(luò)鏈路中。當(dāng)信號到達另一端時，相反的過程將發(fā)生。 6.2.1 數(shù)據(jù)終端設(shè)備 數(shù)據(jù)終端設(shè)備（DTE）包括所有具有作為二進制數(shù)字數(shù)據(jù)源點或終點能力的單元。在物理層，這可以是一臺終端、一臺小型計算機、計算機、打印機、傳真機或