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AT89C2051 Description
The AT89C2051 is a low-voltage, high-performance CMOS 8-bit micr-ocomputer with 2 Kbytes of Flash programmable and erasable read only m-emory (PEROM). The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standar-d MCS-51? instruction set and pinout. By combining a versatile 8-bit CP-U with Flash on a monolithic chip, the Atmel AT89C2051 is a powerful microcomputer which provides a highly flexible and cost effective solutiont-o many embedded control applications.
The AT89C2051 provides the following standard features: 2 Kbytes ofFlash, 128 bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five v-ector two-level interrupt architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator and clock circuitry. In addition, the A-T89C2051 is designed with static logic for operation down to zero freque-ncy and supports two software selectable power saving modes. The Idle M-ode stops the CPU while allowing the RAM, timer/counters, serial port an-d interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functio-ns until the next hardware reset. Pin Configuration：
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverti-ng amplifier which can be configured for use as an on-chip oscillator, as s-hown in Figure 1. Either a quartz crystal or ceramic resonator may beused. To drive the device from an external clock source, XTAL2 should b-eleft unconnected while XTAL1 is driven as shown in Figure 2. There ar-eno requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop,but minimum and maximum voltage high and low time specifications mustbe observed.
Restrictions on Certain Instructions
The AT89C2051 and is an economical and cost-effective member of Atmel’s growing family of microcontrollers. It contains 2 Kbytes of flash program memory. It is fully compatible with the MCS-51 architecture, andcan be programmed using the MCS-51 instruction set. However, there are a few considerations one must keep in mind when utilizing certain instructions to program this device.
All the instructions related to jumping or branching should be restricte-d such that the destination address falls within the physical program mem-ory space of the device, which is 2K for the AT89C2051. This should be the responsibility of the software programmer. For example, LJMP 7E0H would be a valid instruction for the AT89C2051 (with 2K of memory), w-hereas LJMP 900H would not.
1. Branching instructions:
LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR These uncon-ditional branching instructions will execute correctly as long as the progra-mmer keeps in mind that the destination branching address must fall withi-n the physical boundaries of the program memory size (locations 00H to 7FFH for the 89C2051). Violating the physical space limits may cause unkn-own program behavior.
CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ With these c-onditional branching instructions the same rule above applies. Again, violat-ing the memory boundaries may cause erratic execution.
For applications involving interrupts the normal interrupt service routin-e address locations of the 80C51 family architecture have been preserved.
2. MOVX-related instructions, Data Memory:
The AT89C2051 contains 128 bytes of internal data memory. Thus, inthe AT89C2051 the stack depth is limited to 128 bytes, the amount of ava-ilable RAM. External DATA memory access is not supported in this devi-ce, nor is external PROGRAM memory execution. Therefore, no MOVX [...] instructions should be included in the program.
A typical 80C51 assembler will still assemble instructions, even if the-y are written in violation of the restrictions mentioned above. It is the res-ponsibility of the controller user to know the physical features and limitati-ons of the device being used and adjust the instructions used correspondin-gly.
Program Memory Lock Bits
On the chip are two lock bits which can be left unprogrammed (U) o-r can be programmed (P) to obtain the additional features listed in the ta-ble below:
Lock Bit Protection Modes
Program Lock Bits
LB1 LB2
Protection Type
1 U U
No program lock features
2 P U
Further programming of the Flash is disabled.
3 P P
Same as mode 2, also verify is disabled.
Note:1.The Lock Bits can only be erased with the Chip Erase operation
Idle Mode
In idle mode, the CPU puts itself to sleep while all the onchip periph-erals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or b-y a hardware reset.
P1.0 and P1.1 should be set to ’0’ if no external pullups are used, or set to ’1’ if external pullups are used.
It should be noted that when idle is terminated by a hardware reset, t-he device normally resumes program execution, from where it left off, up-to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access tothe port pins is not inhibited. To eliminate the possibility of an unexpectedwrite to a port pin when Idle is terminated by reset, the instruction follow-ing the one that invokes Idle should not be one that writes to a port pin-or to external memory.
Power Down Mode
In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RA-M and Special Function Registers retain their values until the power downmode is terminated. The only exit from power down is a hardware reset.R-eset redefines the SFRs but does not change the onchip RAM. The reset should not be activated before VCC is restored to its normal operatin-g level and must be held active long enough to allow the oscillator to res-tart and stabilize.
P1.0 and P1.1 should be set to ’0’ if no external pullups are used, or set to ’1’ if external pullups are used.
Programming The Flash
The AT89C2051 is shipped with the 2 Kbytes of on-chip PEROM co-de memory array in the erased state (i.e., contents = FFH) and ready to b-e programmed. The code memory array is programmed one byte at a tim-e. Once the array is programmed, to re-program any non-blank byte, the e-ntire memory array needs to be erased electrically.
Internal Address Counter: The AT89C2051 contains an internal PEROM address counter which is always reset to 000H on the rising edge of RST and is advanced by applying a positive going pulse to pin XTAL1.
Data Polling: The AT89C2051 features Data Polling to indicate the end ofa write cycle. During a write cycle, an attempted read of the last byte wri-tten will result in the complement of the written data on P1.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycl-e has been initiated.
Ready/Busy: The Progress of byte programming can also be monitored by the RDY/BSY output signal. Pin P3.1 is pulled low after P3.2 goes Highduring programming to indicate BUSY. P3.1 is pulled High again when pr-ogramming is done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been programmed co-de data can be read back via the data lines for verification:
1. Reset the internal address counter to 000H by bringing RST from’L’to ’H’.
2. Apply the appropriate control signals for Read Code data and read the output data at the port P1 pins.
3. Pulse pin XTAL1 once to advance the internal address counter.
4. Read the next code data byte at the port P1 pins.
5. Repeat steps 3 and 4 until the entire array is read. The lock bits canno-t be verified directly. Verification of the lock bits is achieved by observin-g that their features are enabled.
Chip Erase: The entire PEROM array (2 Kbytes) and the two Lock Bits are erased electrically by using the proper combination of control signals a-nd by holding P3.2 low for 10 ms. The code array is written with all “1-"s in the Chip Erase operation and must be executed before any nonblankmemory byte can be re-programmed.
Reading the Signature Bytes: The signature bytes are read by the same p-rocedure as a normal verification of locations 000H, 001H, and 002H, exc-ept that P3.5 and P3.7 must be pulled to a logic low. The values returne-dare as follows.
(000H) = 1EH indicates manufactured by Atmel
(001H) = 21H indicates 89C2051
Programming Interface：
Every code byte in the Flash array can be written and the entire arra-y can be erased by using the appropriate combination of control signals. T-he write operation cycle is self-timed and once initiated, will automaticallytime itself to completion.
AT89C2051功能特性：
AT89C2051是一種低電壓，高性能CMOS 8位單片機，片內含2k bytes的可反復擦寫的只讀程序存儲器（PEROM）和128 bytes的隨機隨取數(shù)據(jù)存儲器（RAM），器件采用ATMEL 公司的高密度，非易失性存儲技術生產(chǎn)，兼容標準MCS-51指令系統(tǒng)，片內置通用8位中央處理器和Flash 存儲單元，功能強大AT89C2051單片機可為您提供許多高性價比的應用場合。
AT89C2051提供以下標準功能：2k字節(jié)Flash閃速存儲器，128字節(jié)內部RAM，15個I/O口線，兩個16位定時/計數(shù)器，一個5向量兩級中斷結構，一個全雙工串行通信口，內置一個精密比較器，片內振蕩器及時鐘電路。同時，AT89C2051可降至0Hz的表態(tài)邏輯操作，并支持兩種軟件可選的節(jié)電工作模式。空閑方式停止CPU的工作，但允許RAM，定時/計數(shù)器，串行通信及中斷系統(tǒng)繼續(xù)工作。掉電方式保存RAM中的內容，但振蕩器停止工作并禁止其它所有部件工作直到下個硬件復位。引腳結構如下
振蕩器特征：
XTAL1、 XTAL2為片內振蕩器的反相放大器的輸入和輸出端，如下圖所示?？刹捎檬⒕w或陶瓷振蕩器組成時鐘振蕩器，如需從外部輸入時鐘驅動AT89C2051，時鐘信號從XTAL1輸入，XTAL2應懸空。由于輸入到內部電路經(jīng)過一個2分頻觸發(fā)器，所以輸入的外部時鐘信號無需要特殊要求，但它必須符合電平的最大和最小值及時序規(guī)范。
某些指令的約束條件：
AT89C2051是經(jīng)濟型低價位的微控制器，它含有2k字節(jié)的Flash閃速程序存儲器，指令系統(tǒng)與MCS—51完全兼容，可使用MCS—51指令系統(tǒng)對其進行編程。但是在使用某些有關指令編程時，程序員須注意一些事項。
和跳轉或分支有關的指令有一定的空間約束，使目的地址能安全落在AT89C2051的2k字節(jié)的物理程序存儲器空間內，程序員必須注意這一點。對于2k字節(jié)存儲器的AT89C2051來說，LJMP 7E0H是一條有效指令，而LJMP 900H則為無效指令。
1．分支指令：
對于LCALL、LJMP、ACALL、AJMP、SJMP、JMP@+DPTR等指令，只要程序員記住這些分支指令的目的地址在程序存儲器大小的物理范圍內（AT89C2051程序地址空間為：000H—7FFH單元），這些無條件分支就會正確執(zhí)行，超出物理空間的限制會出現(xiàn)不可預知的程序出錯。CJNE[……]、DJNZ[……]、JB、JNB、JC、JNC、JBC、JZ、JNZ等這些條件轉移指令的使用與上述原則一樣，同樣，超出物理空間的限制也會引起不可預知的程序出錯。至于中斷的使用，80C51系列硬件結構中已保留標準中斷服務子程序的地址。
2．與MOVX相關的指令，數(shù)據(jù)存儲器：
AT89C2051包含128字節(jié)內部數(shù)據(jù)存儲器，這樣，AT89C2051的堆棧深度局限于內部RAM的128字節(jié)范圍內，它既不支持外部數(shù)據(jù)存儲器的訪問，也不支持外部程序存儲器的執(zhí)行，因此程序中不應有MOVX[……]指令。
一般的80C51匯編器即使在違反上述指令約束而寫入指令時仍對指令進行匯編，用戶應了解正在使用的AT89C2051微控制器的存儲器物理空間和約束范圍，適當?shù)卣{整所使用的指令尋址范圍以適應AT89C2051。
程序存儲器的加密：AT89C2051可使用對芯片上的兩個加密位進行編程（P）或不編程（U）來得到如下表所示的功能：
空閑模式：
在空閑模式下，CPU保持睡眠狀態(tài)而所有片內的外設仍保持激活狀態(tài)，這種方式由軟件產(chǎn)生。此時，片內RAM和秘有特殊功能寄存器的內容保持不變?？臻e模式可由任何允許的中斷請求硬件復位終止。
P1.0 和P1.1在不使用外部上拉電阻的情況下應設置為”0”，或者在使用上拉電阻的情況下設置為“1”。
應注意的是：在用硬件復位終止空閑模式時，AT89C2051通常從程序停止一直到內部復位獲得控制之前的兩個機器周期處恢復程序執(zhí)行。在這種情況下片內硬件禁止對內部RAM的讀寫，但允許對端口的訪問，要消除萬事硬件復位終止空閑模式對端口意外寫入的可能，原則上進入空閑模式指令的下一條指令不應對端口引腳或外部存儲器進行訪問。
掉電模式：
在掉電模式，振蕩器停止工作，進入掉電模式的指令性計劃是最后一條被執(zhí)行的指令，片內RAM的特殊功能寄存器的內容在終止掉電模式前被凍結。退出掉電模式的唯一方法是硬件復位，復位后將重新定義全部特殊功能寄存器但不改變RAM中的內容，在VCC恢復到正常工作電平前，復位應無效，且必須保持一定時間以使振蕩器重啟動并穩(wěn)定工作。
P1.0 和P1.1在不使用外部上拉電阻的情況下應設置為“0”，或者在使用外部上拉電阻時應設為“1”。
Flash閃速存儲器的編程：
AT89C2051是在擦除狀態(tài)下用2k字節(jié)的片內PEROM代碼存儲陣列封裝微控制器，其程序存儲器是可反復編程的。代碼存儲陣列一次編程一個字節(jié)，一旦陣列被編程，如需重新編程一非空字節(jié)，必須對整個存儲器陣列進行電擦除。
內部址計數(shù)器：AT89C2051內部包含一個PEROM編程地址計數(shù)器，它總在RST上升沿到來時復位到000H，并在XTAL1引腳上出現(xiàn)正跳變脈沖時進行加1計數(shù)。
數(shù)據(jù)查詢：AT89C2051具有寫周期結束的數(shù)據(jù)查詢功能，在寫周期期間，對最后寫入的字節(jié)嘗試將令P1.7上寫入數(shù)據(jù)通信的操作結束。當寫周期完成，全部輸出端的真實數(shù)據(jù)有效，同時下一個周期開始，數(shù)據(jù)查詢可在寫周期被初始化的任一時刻開始。
Ready/Busy：字節(jié)編程的進度可通過“RDY/BSY”輸出信號監(jiān)測，編程期間，P3.1引腳在P3.2變高“H”后被拉低來指示“BSY”，在編程結束后被再次拉高”H”來指示“RDY”。
程序校驗：如果加密LB1、LB2沒有進行編程，則代碼數(shù)據(jù)可通過校驗數(shù)據(jù)線讀?。?
1．使RST從“L”變?yōu)椤癏”，復位內部的地址計數(shù)器為期為000H。
2．對代碼數(shù)據(jù)加上正確的控制信號即可在P1口引腳上讀取數(shù)據(jù)。
3．XTAL1引腳跳變一次使內部地址計數(shù)器加1。
4．從P1口讀取下一個代碼字節(jié)。
5．重復3到4步驟，即可將全部單元的數(shù)據(jù)讀取。加密位不可直接校驗，加密位的校驗可通過對存儲器和校驗和寫入狀態(tài)來驗證。
芯片擦除：利用控制信號的正確組合并保持P3.2引腳10mS的低電平即可將PEROM（2k字節(jié)）陣列和兩個加密位整片擦除，代碼陣列在片擦除操作中將任何非空單元寫入“1”可被再編程之前進行。
讀片內簽名字節(jié)：除P3.25、P3.7必須被拉成邏輯低電平外，讀簽名字節(jié)的過程和單元000H、001H及002H的正常校驗相同，返回值意義如下：
（000H）=1EH聲明產(chǎn)品由ATMEL公司制造。
（001H）=2IH聲明為89C2051單片機。
編程接口：Flash閃速陣列中的每一代碼字節(jié)進行寫入且整個存儲器可在控制信號的正確組合下進行擦除，寫操作周期是自身寫時的，初始化后它將自動定時到操作完成。
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