英文原文 Journal of Software Engineering and Applications 2011 4 172 180 doi 10 4236 jsea 2011 43019 Published Online March 2011 http www SciRP org journal jsea Development of Equivalent Virtual Instruments to PLC Functions and Networks Mohammad A K Alia Tariq M Younes Mohammad Abu Zalata Mechatroncis Engineering Department Faculty of Engineering Technology Al Balqa Applied University Amman Jordan Email makalalia2000 tariqmog abuzalata Received February 20th 2011 revised March 5th 2011 accepted March 10th 2011 ABSTRACT This research is a continuation to our work which was published in 1 Eight different timing VIs are designed and tested These include ON Delay OFF Delay Single Shot Retriggerable Monostable and Accumulative software based timers Using hardware programmable counter timer chip DAQ STC 24bit and PCI MIO 16E 1 DAQ board another two precise timers are designed At the end of the paper for illustration purposes an electro pneumatic drive system was developed and controlled utilizing designed on delay timers VI functions Results of experiment show complete coincidence between the PLC based control and Virtual PLC based program results Keywords PLC Virtual PLC LabVIEW Programmable Timers 1 Introduction In our work Design of a virtual PLC using LabVIEW we have shown how it is possible to create LabVIEW VIs which represent PLC functions and networks We compared between PC based and PLC based control systems and came to the fact that both systems are continuously developing in the same direction in order to obtain better programmability connectivity and communication interfacing At the time being the PC based DCSs are suited for industrial applications They are robust and they easily work in an open architecture mode while PLCs are equipped with specific MMI software and pseudo standard commutation software also We have shown that in order to improve the programmability of PACs we practically brought the PLC to the computer utilizing by that numerous advantages of computers such as multitasking unlimited memory high speed and the possibility of creating unlimited number of programmable objects such as counters timers shift registers and others Because of the limited size of previous work we were not able to cover other important VIs which may be used also as the analog of PLC functions In this paper we shall develop different types of programmable timers using LabVIEW software 2 and NI DAQ board hardware also The LabVIEW basic functions that provide timing on millisecond level are the wait and wait for Next ms Multiple VIs Both are based on the same under lying mechanism Most applications work comfortably with available LabVIEW measurements that resolve milliseconds and many more operate with second resolution 3 4 A few applications demand sub millisecond resolution and response time which is problematic due primarily to operating system and not a LabVIEW limitation 5 If the application requires higher accuracy or resolution than the built in timing functions can supply then one will have to use some additional hardware such as NI DAQ boards or an external clock 6 NI boards have two 24bit counter chips and several on board clocks that can be counted to produce accurate timing intervals With the DAQ counter timer VIs one can configure the on board versatile hardware for a variety of tasks including the accurate generation of timed pulses counting events and the measurement of periods and frequencies The counter output generates a pulse when a preprogrammed terminal count TC is reached The pulse may be used for sequencing purposes Similar hardware based timing may be performed using windows API function Query performance counter This function looks at a high resolution system hardware counter that runs at approximately 1 2 MHz or 0 8 microsecond count The actual resolution once we account for the delay in calling the function will be considerably less but still far better than one millisecond Concerning Real Time operating systems RTOS they are designed to run a single program with very precise timing They can allow to run loops with nearly the same thing each iteration typically within microseconds Timing for hard RTOSs can be performed using the DAQ card s internal clock giving better accuracy than software timing functions 7 At the time being some hardware platforms feature an on board FPGA that may be programmed using LabVIEW FPGA module NI ComactRIO and single board RIO are examples The default clock rate of LabVIEW FPGA is 40 MHz General FPGA timing VIs 2 may generate one clock period One shot pulse or measure the period pulse width accumulate period over a specified number of pulses and count pulses over a specified period of time Nevertheless FPGA VIs do not include ready On delay timers OFF delay timers and momostable retriggerable timers which find extensive applications in PLC sequential control programs Building on the above the target of this work is to illustrate the design of different types of timing VIs using LabVIEW software in order to be used as programming elements in virtual PLC programs 2 ON Delay Timer 1 ON Delay Timer 1 Figure 1 shows the front panel and the block diagram components of a software based ON Delay Timer The loop iteration is indicated in seconds Because the loop iteration starts from zero the increment function is added in order to start it at one Since the wait icon has 100 ms delay between every two iterations a factor of 10 is multiplied by timer preassigned value in order to measure the time delay in seconds After the application of enable signal it takes some delay time interval for the equal function to have a true state at the output If the input signal is disabled the timer output instantly changes to low state 2 ON Delay Timer 2 The components of the VI are shown in the block diagram Figure 2 Initially the input signal is not enabled and the false case is activated The output of select icon will be zero which is lower than the timer preset value and as a result of that the output of the timer is OFF When the input signal is enabled the true case is executed and the select icon will output the value that comes form the output of the case structure The initial value of the iteration local variable is zero then it will be incremented after a delay caused by the wait icon and then compared by timer preset value When the output of the comparison function is true the output of the timer becomes high When the enable input signal becomes low the output of the timer becomes low simultaneously In this VI the checking of the case structure is continuous at a scan rate equal to one millisecond which is accepted for many applications a b c Figure 1 On delay timer 1 a The Block Diagram b The Front Panel c Subicon 3 OFF Delay Time 1 OFF Delay Timer 1 The front panel and block diagram are shown in Figure3 The while loop and other VI components are located inside the false case of the case structure The true case has a local variable of the timer output which is wired to the selector terminal The enable input signal is connected to the selector terminal of the false case 2 OFF Delay Timer 2 The block diagram is given in Figure 4 When the input is enabled the true case is activated and the select icon will be selected to zero In this case the output of the comparison function is false and the timer output is true When the input signal is disabled the false case executes and the select icon is selected to the value that comes from the output of the case structure When the off delay time interval elapses the output of the comparison function is true and the timer output is false a b Figure 4 OFF delay timer 4 a True case b False case 4 Single Shot Timer The block diagram and front panel are shown in Figure 5 The Boolean indicator prevents the timer output to turn ON again after the elapse of the preset value of one shot timer During the false case the output is OFF and during the comparison time the timer output enabled high At the end of comparison the timer output is low again 5 Retriggerable Monostable Timer VI Figure 6 shows the block diagram and the front panel of this timer When the enable input switches ON the timer output immediately turns ON and the timer starts timing As soon as the preset time value has elapsed the timer output switches OFF even if the enable input is still ON Every OFF to ON transition of the enable input resets the timer i e the elapsed time is set to pre set value and timer output is switched ON Figure 7 shows a three mode delay timer ON delay OFF delay and Retriggerable Monostable timers are built in one block diagram where the programmer can select the required timer mode 6 Accumulative Timer VI The timer block diagram and front panel are shown in Figure 8 The output of the add function and the timer preset value are connected to the equal comparison function The output equal comparison function is connected to one terminal of the OR gate The other input of the OR gate function is connected to the inverted input signal The output of OR function is connected to conditional terminal of the while loop a b c Figure 3 OFF delay timer a The block diagram b The front panel c Subicon The conditional terminal is connected to one terminal of the AND gate The other input of the AND gate is connected to local variable of the input signal The output of the AND gate is the timer output The while loop and above mentioned components are inside the true case of the case structure When the input signal is not enabled the false case is activated then the local variable of accumulative indicator has a zero value and that value will be stored in the current time indicator The true case will be activated when the input signal is enabled If the input signal is disabled before the equal comparison function is true the false case is activated and the local variable of the loop iteration has that value at which the loop was stopped and this value will be stored in the current time indicator If the input signal is activated again the true case is activated and the previous operation is repeated again where the loop iteration is added to the previous value which is stored in the current timer indictor then it is compared with the timer preset value The process of enabling and displaying the input signal continues until the output of the equal comparison function becomes true and as a result the timer output turns ON Figure 9 shows a designed VI in order to measure time interval in the range of nanoseconds A hardware programmable counter timer chip DAQSTC 24 bit and a hardware time base signal source located on PCI MIO 16E 1 DAQ Board are utilized The program is built using the advance subVIs because they are more flexible than the easy VIs or intermediate VIs A closely related issue is the use of two hardware counters for measurement of sampling time interval In such a case the signal of interest is fed to a counter source terminal and to the gate terminal of another counter The source terminal of the second counter is fed by a periodic clock signal with a much higher frequency than the expected sampling frequency Normally the internal time base of the counter provides more than adequate source to count i e 20 MHZ and above To receive an accurate indication of the time both counters must start at the same instant By diving the count of the second counter by the frequency we find the time As an example we shall consider an electro pneumatic drive system The drive circuit is given in Figure 10 PLC input output assignments are given in Table 1 Input output channels assignment for LabVIEW DAQboard are given in Table 2 System operation sequence is as follows In order to initialize operation an external pushbutton is used As a result of that solenoid valve SV is energized and cylinder out strokes At the end of stroke the cylinder actuates limit switch LS which enables an ON Delay timer T1 After the elapse of the timer preset time value the SV is deenergized and returns to its initial position At this instance ON Delay timer T2 is enabled up counter CTU is incremented the timer T1 is disabled and the solenoid valve is actuated again and the sequence repeats The sequence is continued until the counter instantaneous count is equal to counter preset value and the sequence stops For Siemens PLC S7 214 the ladder diagram is shown in Figure 11 and the equivalentLabVIEW ladder diagram is shown in Figure 12 Experimental results show completely coincidence between both diagrams 7 Conclusions Using LabVIEW environment seven different timing virtual instruments have been designed and tested Applying the same approach it is possible to design a complete set of PLC functions in order to realize able PC based virtual PLC In this case the virtual PLC will gain the advantages of PC Based control REFERENCES 1 M K Abuzalata M A Alia et al Designing Virtual PLC Using LabVIEW Applied Sciences Engineering and Technology Maxwell Science Publication UK Vol 2 No 3 2010 p 288 2 Function and VI Reference Manual National Instruments 1998 Edition Austin USA 3 K L A Shley Analog Electronics with LabVIEW Prentice Hall PTR 2003 4 T Mohioddin and M Nawroki LabVIEW Advance Programming Techniques Second Edition CRC Press Boca Raton 2006 5 J Essick Hands on Introduction to LabVIEW for Scientists and Engineers Oxford University Press USA 2008 6 J Y Beyon Hands on Exercise Manual for LabVIEW Programming Data Acquisition and Analysis Prentice Hall PTR USA 2003 7 B E Paton Sensors Transducers and LabVIEW Prentice Hall International UK Limited London 1993 中文譯文 軟件工程與應(yīng)用 學(xué)報(bào) 2011 4 172 180 開發(fā)與 PLC 功能和網(wǎng)絡(luò)等效的虛擬儀器 Mohammad A K Alia Tariq M Younes Mohammad Abu Zalata Received February 20th 2011 revised March 5th 2011 accepted March 10th 2011 摘要 本研究是對(duì)我們工作的一個(gè)延續(xù) 發(fā)表在 1 設(shè)計(jì)和測試了八個(gè)不同的時(shí)間 VIs 這包括延遲打 開 延遲斷開 單發(fā)射擊 可在觸發(fā)的單穩(wěn)態(tài) 累計(jì)計(jì)時(shí)器軟件 使用硬件可編程計(jì)數(shù)器 定時(shí)器芯片 設(shè)計(jì) DAQ STC 24bit 和 PCI MIO 16E 1 DAQ 板兩個(gè)精確的計(jì)時(shí)器 在本文的結(jié)尾 開發(fā)一個(gè)電動(dòng)氣動(dòng) 驅(qū)動(dòng)系統(tǒng)和利用對(duì)延遲計(jì)時(shí)器控制設(shè)計(jì) VI 功能 來解釋 實(shí)驗(yàn)結(jié)果顯示基于 plc 程序控制和基于 plc 虛擬兩者之間的結(jié)果是一致的 關(guān)鍵詞 可編程控制器 PLC 虛擬 虛擬儀器 可編程定時(shí)器 1 介紹 我們的工作 使用虛擬儀器設(shè)計(jì)虛擬 PLC 我們已經(jīng)表明我們可以創(chuàng)建代表的 PLC 功能和網(wǎng)絡(luò)的 虛擬儀器 我們比較基于 PC 和基于 PLC 的控制系統(tǒng) 來得到兩個(gè)系統(tǒng)不斷在同一方向發(fā)展以取得更 好的可編程性 連通性和連通接口 同時(shí)基于 PC 的 DCSs 是適合工業(yè)應(yīng)用的 他們是健大的和他們輕 松地工作在一個(gè)開放的架構(gòu)模式 雖然 PLC 是配備特定的 MMI 軟件和偽標(biāo)準(zhǔn)變換軟件 我們表明 為了 提高的可編程性 PACs 我們幾乎把計(jì)算機(jī)的眾多優(yōu)點(diǎn)的 PLC 作為多任務(wù) 無限的記憶 高速和可能創(chuàng)造 出無限數(shù)量的可編程對(duì)象如計(jì)數(shù)器 計(jì)時(shí)器 移位寄存器和其他 因?yàn)橹暗墓ぷ饕?guī)模有限 我們不能 覆蓋其他重要的工作 使用和模擬 PLC 功能 本文我們開發(fā)不同類型的使用虛擬儀器軟件 2 和 NI DAQ 板硬件的可編程定時(shí)器 虛擬儀器的基本功能 提供時(shí)間在毫秒級(jí)的 等待 和 等待多個(gè) VIs 兩者都是基于相同的底層機(jī)制 大多數(shù)應(yīng)用程序工作的舒適 可用虛擬儀器測量 解決毫秒 更 多的操作與第二分辨率 3 4 一些應(yīng)用程序的需求和響應(yīng)時(shí)間毫秒級(jí)的決議 這是有問題的 主要是 由于操作系統(tǒng) 而不是一個(gè)虛擬儀器限制 5 一些應(yīng)用程序的需求和響應(yīng)時(shí)間毫秒級(jí)的決議 這是有問 題的 主要是由于操作系統(tǒng) 而不是一個(gè)虛擬儀器限制 5 如果應(yīng)用程序需要更高的精度和分辨率比內(nèi) 置定時(shí)功能可以供應(yīng) 那么你將不得不使用一些額外的硬件 比如我董事會(huì)或外部時(shí)鐘 6 鎳板有兩個(gè) 24 位計(jì)數(shù)器芯片和一些船上的時(shí)鐘 可以算出精確定時(shí) 時(shí)間間隔 與 DAQ 計(jì)數(shù)器定時(shí)器 VIs 一個(gè)可 以配置車載多功能硬件來完成各種任務(wù) 包括精確定時(shí) 計(jì)數(shù)脈沖生成事件 和測量時(shí)間和頻率 產(chǎn)生一 個(gè)脈沖計(jì)數(shù)器輸出當(dāng)預(yù)排程序的終端數(shù) TC 是達(dá)到了 脈沖可以用于排序的目的 類似的基于硬件的 時(shí)機(jī)可能是使用 windows API 函數(shù)進(jìn)行 查詢性能計(jì)數(shù)器 這個(gè)函數(shù)看起來在一個(gè)高分辨率的系統(tǒng) 硬件計(jì)數(shù)器運(yùn)行大約在 1 2 MHz 或 0 8 微秒數(shù) 實(shí)際的分辨率 一旦我們帳戶延期 調(diào)用該函數(shù) 將大大 減少 但仍遠(yuǎn)比一個(gè)毫秒 關(guān)于實(shí)時(shí)操作系統(tǒng) RTOS 它們被設(shè)計(jì)為運(yùn)行一個(gè)程序非常精確定時(shí) 他們 可以允許運(yùn)行循環(huán)幾乎同樣的事情每個(gè)迭代 通常在微秒 硬 RTOSs 時(shí)機(jī)可以執(zhí)行使用 DAQ 卡的內(nèi)部 時(shí)鐘 給予更好的精度比軟件定時(shí)功能 7 當(dāng)時(shí) 一些硬件平臺(tái)功能的 FPGA 這可能是使用 FPGA 模塊 編程虛擬儀器 NI ComactRIO 和單板是例子 默認(rèn)的時(shí)鐘頻率的 FPGA 是 40 MHz 虛擬儀器 通用 FPGA 定時(shí) VIs 2 可能會(huì)生成一個(gè)時(shí)鐘周期 一次性脈沖或測量周期 脈沖寬度 積累期超過指定數(shù)量的脈 沖和計(jì)數(shù)脈沖在指定的一段時(shí)間 然而 FPGA VIs 不包括準(zhǔn)備在延遲定時(shí)器 定時(shí)器和 momostable 延遲 斷開可再觸發(fā)的計(jì)時(shí)器 找到廣泛應(yīng)用于 PLC 順序控制程序 建立在上面的 這個(gè)工作的目標(biāo)是說明設(shè) 計(jì)不同類型的定時(shí) VIs 使用虛擬儀器軟件為了被用作編程元素在虛擬 PLC 程序 2 接通延時(shí)時(shí)間 1 接通延時(shí) 1 圖 1 顯示了前面板和程序框圖的組件軟件在延遲計(jì)時(shí)器 循環(huán)迭代顯示秒 由于循環(huán)迭代開始從 零 增加功能被添加以啟動(dòng)它在一個(gè) 因?yàn)榈却龍D標(biāo)有 100 毫秒的延遲每兩個(gè)迭代之間的 10 倍乘以定 時(shí)器預(yù)先指定的值 為了測量時(shí)間延遲在秒 應(yīng)用程序的啟動(dòng)信號(hào)后 它需要一些延遲時(shí)間間隔相等的 功能有一個(gè)真正的狀態(tài)輸出 如果輸入信號(hào)是禁用的 定時(shí)器輸出立即改變低狀態(tài) 2 接通延時(shí) 2 VI 的組件顯示在框圖 2 最初輸入信號(hào)不啟用和虛假的情況下被激活 選擇圖標(biāo)的輸出是 0 即低 于預(yù)設(shè)值 定時(shí)器的結(jié)果是輸出的計(jì)時(shí)器是關(guān)閉的 當(dāng)輸入信號(hào)是使真正的案件執(zhí)行 選擇圖標(biāo)將輸出 值 來自輸出案例的結(jié)構(gòu) 迭代初始值的局部變量是零 那么它將增加所造成的延遲后等待圖標(biāo) 然后由 定時(shí)器預(yù)設(shè)值相比 當(dāng)比較函數(shù)的輸出是正確的 輸出的定時(shí)器就高 當(dāng)允許輸入信號(hào)就低 輸出的計(jì) 時(shí)器同時(shí)就低 在這個(gè) VI 檢查案例的結(jié)構(gòu)是連續(xù)在一個(gè)掃描速率等于一毫秒 接受許多應(yīng)用程序 a b 3 在延遲定時(shí)器 a 框圖 b 面板 c 功能 3 關(guān)閉延時(shí) 1 關(guān)閉延時(shí) 1 前面板和方塊圖是圖 3 所示 當(dāng)循環(huán)和其他 VI 組件的位置在錯(cuò)誤的情況下的情況下結(jié)構(gòu) 真實(shí)的 案例有一個(gè)局部變量定時(shí)器的輸出 這是連接到選擇器終端 允許輸入的信號(hào)連接到選擇器終端的虛假 情況 2 關(guān)閉延時(shí) 2 給出了框圖如圖 4 當(dāng)輸入是啟用的情況下被激活的真實(shí)和選擇圖標(biāo)將被選定為零 在這種情況 下 輸出的比較函數(shù)是假和定時(shí)器輸出是正確的 當(dāng)輸入信號(hào)是禁用的虛假案件執(zhí)行 選擇圖標(biāo)被選中 的值來自輸出案例的結(jié)構(gòu) 當(dāng)關(guān)閉延遲時(shí)間間隔過后比較函數(shù)的輸出是真的和定時(shí)器輸出是假的 a b a 真 b 假 4 單發(fā)定時(shí)器 和前面板的框圖如圖 5 所示 布爾指示器防止定時(shí)器輸出后再打開的推移預(yù)設(shè)值一次性計(jì)時(shí)器 在錯(cuò)誤的情況下 輸出是關(guān)閉的 在比較時(shí)間定時(shí)器輸出使高 最后比較計(jì)時(shí)器再次低輸出 5 可再觸發(fā)的單穩(wěn)態(tài)定時(shí)器 VI 圖 6 顯示了框圖和前面板的計(jì)時(shí)器 當(dāng)允許輸入開關(guān) 定時(shí)器輸出立即打開 計(jì)時(shí)器開始計(jì)時(shí) 一 旦預(yù)定時(shí)間價(jià)值已經(jīng)運(yùn)行 定時(shí)器輸出開關(guān)關(guān)閉 即使允許輸入仍在 每一個(gè)去在過渡的允許輸入重置 計(jì)時(shí)器 即運(yùn)行時(shí)間設(shè)置為預(yù)設(shè)值 定時(shí)器輸出接通 圖 7 顯示了一個(gè)三模延遲計(jì)時(shí)器 在延遲 延遲斷 開和可再觸發(fā)的單穩(wěn)態(tài)計(jì)時(shí)器是建立在一個(gè)框圖 程序員可以選擇所需的定時(shí)器模式 6 累計(jì)計(jì)時(shí)器 vi 計(jì)時(shí)器框圖和前面板如圖 8 所示 添加函數(shù)的輸出和計(jì)時(shí)器預(yù)設(shè)值是連接到平等的比較函數(shù) 輸 出相等的比較函數(shù)連接到一個(gè)終端的或門 的另一個(gè)輸入或門函數(shù)連接到反向輸入信號(hào) 或函數(shù)的輸 出終端連接到有條件的 while 循環(huán) a b c a 框圖 b 前面板 c 功能 有條件的終端連接到一個(gè)終端的和門 其他輸入的與門連接到本地變量的輸入信號(hào) 與門的輸出 是定時(shí)器輸出 while 循環(huán)和上述組件是在真實(shí)情況下案例的結(jié)構(gòu) 當(dāng)輸入信號(hào)是不啟用虛假情況下 被激活 那么局部變量的累積指標(biāo)有一個(gè)零值 這個(gè)值將被存儲(chǔ)在當(dāng)前時(shí)間指示器 真實(shí)的情況下將啟 動(dòng)時(shí)的輸入信號(hào)是啟用的 如果輸入信號(hào)是殘疾人平等比較函數(shù)之前是正確的 錯(cuò)誤的情況下被激活和 本地變量的循環(huán)迭代有價(jià)值的循環(huán)停止 這個(gè)值將被存儲(chǔ)在當(dāng)前時(shí)間指示器 如果輸入信號(hào)被再次激活 真 正的情況下被激活和前面的操作再次重復(fù) 循環(huán)迭代添加到之前的值 這是存儲(chǔ)在當(dāng)前的定時(shí)器起訴者 那么它就是與計(jì)時(shí)器預(yù)設(shè)值 流程的建立及顯示輸入信號(hào)持續(xù)進(jìn)行直到輸出相等的比較函數(shù) 結(jié)果變成 真正的定時(shí)器輸出打開 硬件可編程計(jì)數(shù)器 定時(shí)器芯片 DAQSTC 24 鉆頭 和硬件時(shí)基信號(hào)來源位于 PC I MIO 16E 1 板是利用 該計(jì)劃是建立采用先進(jìn) subVIs 因?yàn)樗麄兏`活的比容易 VIs 或中間 vi 一個(gè) 密切相關(guān)的問題是使用兩個(gè)硬件計(jì)數(shù)器測量的采樣時(shí)間間隔 在這種情況下信號(hào)的興趣喂養(yǎng)計(jì)數(shù)器源 終端和終端的另一個(gè)計(jì)數(shù)器 源終端的第二個(gè)計(jì)數(shù)器是美聯(lián)儲(chǔ)通過定期時(shí)鐘信號(hào)具有更高的頻率比預(yù) 期的采樣頻率 正常情況下 內(nèi)部的時(shí)基的計(jì)數(shù)器提供超過足夠的源數(shù) 即 20 MHZ 以上 得到一個(gè)精 確的指示的時(shí)間 兩個(gè)計(jì)數(shù)器必須開始在同一瞬間 由潛水的計(jì)數(shù)第二計(jì)數(shù)器的頻率我們找時(shí)間 作為 一個(gè)例子 我們將考慮一個(gè)電控驅(qū)動(dòng)系統(tǒng) 給出了驅(qū)動(dòng)電路如圖 10 PLC 輸入 輸出作業(yè)是表 1 中給出 輸入 輸出通道分配虛擬儀器 DAQ 板給出了表 2 系統(tǒng)操作順序如下 為了初始化操作使用一個(gè)外部 的按鈕 因此 電磁閥 SV 是精力充沛和缸 最后的行程氣缸驅(qū)動(dòng)型限位開關(guān) LS 使一個(gè)在延遲計(jì)時(shí) 器 T1 推移后計(jì)時(shí)器預(yù)定時(shí)間值 SV 斷開并返回到其原始位置 在這個(gè)實(shí)例在延遲計(jì)時(shí)器 T2 已啟 用 計(jì)數(shù)器 定時(shí)器的反恐組增加 T1 是禁用的 電磁閥驅(qū)動(dòng)的序列重復(fù)一遍又一遍 這個(gè)序列是一直持 續(xù)到柜臺(tái)瞬時(shí)計(jì)數(shù)等于計(jì)數(shù)器預(yù)設(shè)值和順序結(jié)束 對(duì)西門子 PLC s7 214 梯形圖如圖 11 所示 梯形 圖如圖 12 實(shí)驗(yàn)結(jié)果表明完全符合兩個(gè)關(guān)系圖 7 結(jié)論 使用虛擬儀器環(huán)境 七種不同的定時(shí)虛擬儀器設(shè)計(jì)和測試 運(yùn)用同樣的方法可以設(shè)計(jì)一套完整的 P LC 功能以實(shí)現(xiàn)能夠基于 pc 的虛擬 PLC 在這種情況下 虛擬 PLC 將獲得的優(yōu)勢(shì) 基于 pc 的控制 參考文獻(xiàn) 1 M K Abuzalata M A Alia et al Designing Virtual PLC Using LabVIEW Applied Sciences Engineering and Technology Maxwell Science Publication UK Vol 2 No 3 2010 p 288 2 Function and VI Reference Manual National Instruments 1998 Edition Austin USA 3 K L A Shley Analog Electronics with LabVIEW Prentice Hall PTR 2003 4 T Mohioddin and M Nawroki LabVIEW Advance Programming Techniques Second Edition CRC Press Boca Raton 2006 5 J Essick Hands on Introduction to LabVIEW for Scientists and Engineers Oxford University Press USA 2008 6 J Y Beyon Hands on Exercise Manual for LabVIEW Programming Data Acquisition and Analysis Prentice Hall PTR USA 2003 7 B E Paton Sensors Transducers and LabVIEW Prentice Hall International UK Limited London 1993